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S i 3 2 1 0 / S i 3 2 11 / S i 3 2 1 2
PR O S L I C TM PR O G R A M M A B L E CMOS SL IC /C O D E C W I T H R I N G I N G / BA T T E R Y VOLTA G E G E N E R A T I O N
Features
Programmable Constant Current Feed (20-41 mA) Programmable Loop Closure and Ring Trip Thresholds with Debouncing Loop or Ground Start Operation and Battery Reversal Continuous Line Voltage and Current Monitoring DTMF Decoder Dual Tone Generator SPI and PCM Bus Digital Interfaces with Programmable Interrupt for Control and Data 3.3 V or 5 V Operation Multiple Loopback Modes for Testing Pulse Metering FSK Caller ID Generation
! ! ! ! !
Ordering Information See page 119.
!
Pin Assignments
SI3210/11/12
CS INT PCLK DRX DTX
! ! !
P P ro ro S S LIC LI C
FSYNC RESET SDCH/DIO1 SDCL/DIO2 VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC STIPE SVBAT SRINGE
!
Performs all Battery, Overvoltage, ! Ringing, Supervision, Coding, Hybrid, and Test (BORSCHT) Functions ! Ideal for Short Loop Applications (5 REN at 2 kft, 3 REN at 4 kft) ! Low Voltage CMOS Package: 38-Pin TSSOP ! Compliant with Relevant LSSGR and CCITT Specifications ! Battery Voltage Generated Dynamically ! with On-Chip DC-to-DC Converter ! Controller (SI3210 only) 5 REN Ringing Generator " Programmable Frequency, Amplitude, ! Waveshape, and Cadence ! Programmable AC Impedance ! A-Law/-Law, Linear PCM Companding ! On-Hook Transmission
Applications
!
Terminal Adaptors ! Cable Telephony ! PBX/Key Systems
!
Wireless Local Loop ! Voice Over IP ! Integrated Access Devices
Description
The ProSLICTM is a low-voltage CMOS device that offers SLIC and codec functionality for a complete analog telephone interface, integrating functions previously requiring multiple devices in multiple technologies. The device is intended for short loop applications such as terminal adaptors, cable telephony, and wireless local loop. The SI3210 is powered with a single 3.3 V or 5 V supply. The SI3210 generates battery voltages dynamically using a software programmable DC-to-DC converter from a 5 V to 30 V supply; negative high-voltage supplies are not needed. All high-voltage functions are performed locally with a few low-cost discrete components. The device is available in a 38-pin TSSOP and interfaces directly to standard SPI and PCM bus digital interfaces.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
SCLK SDI SDO SDITHRU
DCDRV/DCSW
DCFF/DOUT TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP GNDA IGMN SRINGAC STIPAC
Functional Block Diagram
IN T R E SET
S i3210/11/12
L in e Status
Patents pending
TIP
CS SC LK SD O SD I DTX C o n tro l In te rfa ce DTMF D e cod e
Compression
G a in / Atte nu a tio n / Filter To n e G e ne ra to r G a in / Atte nu a tio n / Filter
A/D
DRX
PC M In te rfa ce
Prog ra m H yb rid
L in e Fe e d C o n tro l
L ow C o st Extern a l D iscre te s
FS YN C
Expansion
D /A
ZS R IN G
PC LK
PL L
D C - D C C o n ve rter C o ntrolle r (S i3 21 0 on ly)
Preliminary Rev. 0.9 11/00
Copyright (c) 2000 by Silicon Laboratories
SI3210-DS09
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3 21 0/Si3 211/Si321 2
2
Preliminary Rev. 0.9
SI3210/Si3211/Si3212 TA B L E O F CON T E N T S
Section Page
4 22 22 28 32 34 38 39 40 43 43 43 44 47 48 51 109 109 111 112 113 114 116 119 120 122
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Metering Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DTMF Decoding (SI3210 and Si3211 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI3210/11/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.9
3
Si3 21 0/Si3 211/Si321 2
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature Ambient Temperature SI3210/11/12 Supply Voltage, Analog SI3210/11/12 Supply Voltage, Digital Symbol TA TA VDDA VDDD Test Condition K-grade B-grade Min* 0 -40 3.13 3.13 Typ 25 25 3.3/5.0 3.3/5.0 Max* 70 85 5.25 5.25 Unit
o o
C C
V V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 oC unless otherwise stated. Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used.
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Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Table 2. AC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Overload Level Single Frequency Distortion
1
Test Condition TX/RX Performance THD = 1.5% 2-wire - PCM or PCM - 2-wire: 200 Hz - 3.4 kHz 200 Hz to 3.4 kHz D/A or A/D 8-bit Active off-hook, and OHT, any ZAC 0 dBm0, Active off-hook, and OHT, any Zac 2-wire to PCM, 1014 Hz PCM to 2-wire, 1014 Hz
Min 2.5 --
Typ -- --
Max -- -45
Unit VPK dB
Signal-to-(Noise + Distortion) Ratio2
Figure 1
--
--
Audio Tone Generator Signal-to-Distortion Ratio2 Intermodulation Distortion Gain Accuracy2
45 -- -0.5 -0.5 Figure 3,4 Figure 5,6
-- -- 0 0 -- --
-- -41 0.5 0.5 -- --
dB dB dB dB
Gain Accuracy Over Frequency Group Delay Over Frequency Gain Tracking
3
1014 Hz sine wave, reference level -10 dBm signal level: 3 dB to -37 dB -37 dB to -50 dB -50 dB to -60 dB -0.25 -0.5 -1.0 -- -0.017 -0.25 -0.1 30 30 -- -- -- 40 40 40 -- -- -- -- -- -- -- 35 -- -- -- -- -- -- -- 0.25 0.5 1.0 600 0.017 0.25 0.1 -- -- 15 -75 18 -- -- -- dB dB dB s dB dB dB dB dB dBrnC dBmP dBrn dB dB dB
Round-Trip Group Delay Gain Step Accuracy Gain Variation with Temperature Gain Variation with Supply 2-Wire Return Loss Transhybrid Balance Idle Channel Noise4
Within same time-slot -6 dB to 6 dB All gain settings VDDA = VDDA = 3.3/5 V 5% 200 Hz to 3.4 kHz 300 Hz to 3.4 kHz Noise Performance C-Message Weighted Psophometric Weighted 3 kHz flat
PSRR from VDDA PSRR from VDDD PSRR from VBAT
RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz RX and TX, DC to 3.4 kHz
Preliminary Rev. 0.9
5
Si3 21 0/Si3 211/Si321 2
Table 2. AC Characteristics (Continued)
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Longitudinal to Metallic or PCM Balance
Test Condition Longitudinal Performance 200 Hz to 3.4 kHz, Q1,Q2 150, 1% mismatch Q1,Q2 = 60 to 2405 Q1,Q2 = 300 to 800
5
Min 56 43 53 40
Typ 60 60 60 --
Max -- -- -- --
Unit dB dB dB dB
Metallic to Longitudinal Balance Longitudinal Impedance
200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register selectable
ETBO/ETBA
00 01 10 Longitudinal Current per Pin Active off-hook 200 Hz to 3.4 kHz Register selectable
ETBO/ETBA
-- -- --
33 17 17
-- -- --

00 01 10
-- -- --
4 8 8
-- -- --
mA mA mA
Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be -10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 dB to -37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed -55 dBm. 5. Assumes normal distribution of betas.
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Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Figure 1. Transmit and Receive Path SNDR
9 8 7 6
Fundamental Output Power 5 (dBm0) Acceptable Region
4 3
2.6
2 1 0 1 2 3 4 5 6 7 8 9
Fundamental Input Power (dBm0)
Figure 2. Overload Compression Performance
Preliminary Rev. 0.9
7
Si3 21 0/Si3 211/Si321 2
Typical Response
Typical Response
Figure 3. Transmit Path Frequency Response
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Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Typical Response
Typical Response
Figure 4. Receive Path Frequency Response
Preliminary Rev. 0.9
9
Si3 21 0/Si3 211/Si321 2
s
Typical Response
Figure 5. Transmit Group Delay Distortion
s
Typical Response
Figure 6. Receive Group Delay Distortion
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Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Table 3. Linefeed Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Loop Resistance Range DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance DC Open Circuit Voltage-- Ground Start DC Output Resistance-- Ground Start DC Output Resistance-- Ground Start Loop Closure/Ring Ground Detect Threshold Accuracy Ring Trip Threshold Accuracy Ring Trip Response Time Ring Amplitude Ring DC Offset Trapezoidal Ring Crest Factor Accuracy Sinusoidal Ring Crest Factor Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Power Alarm Threshold Accuracy
Symbol RLOOP
Test Condition See note.* ILIM = 29 mA, ETBA = 4 mA Active Mode; VOC = 48 V, VTIP - VRING
Min 0 -10 -4 -- -4 -- 150 -20 -20 -- 44 0 -.05 1.35
Typ -- -- -- 160 -- 160 -- -- -- -- -- -- -- -- -- -- -- --
Max 160 10 4 -- 4 -- -- 20 20 -- -- -- .05 1.45 1 50 600 25
Unit % V V k % %
RDO VOCTO RROTO RTOTO
ILOOP < ILIM IRINGVTR ROS
5 REN load; sine wave; RLOOP = 160 , VBAT = -75 V Programmable in Indirect Register 19 Crest factor = 1.3
VRMS V
RCF f = 20 Hz Accuracy of ON/OFF Times CAL to CAL Bit At Power Threshold = 300 mW
-1 -50 -- -25
% msec msec %
*Note: DC resistance round trip; 160 corresponds to 2 kft 26 gauge AWG.
Preliminary Rev. 0.9
11
Si3 21 0/Si3 211/Si321 2
Table 4. Monitor ADC Characteristics
(VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Differential Nonlinearity (6-bit resolution) Integral Nonlinearity (6-bit resolution) Gain Error (voltage) Gain Error (current)
Symbol DNLE INLE
Test Condition
Min -1/2 -1 -- --
Typ -- -- -- --
Max 1/2 1 10 20
Unit LSB LSB % %
Table 5. DC Characteristics, VDDA = VDDD = 5.0 V
(VDDA,VDDD = 4.75 V to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage
Symbol VIH VIL VOH
Test Condition
Min 0.7 VD
"
Typ -- -- -- -- --
Max -- 0.3 VD
"
Unit V V V V V
--
DIO1,DIO2,SDITHRU:IO = -4 mA VD - 0.6 SDO, DTX:IO = -8 mA DOUT: IO = -40 mA
-- -- 0.4
VD - 0.8 --
Low Level Output Voltage
VOL
DIO1,DIO2,DOUT,SDITHRU: IO = 4 mA SDO,INT,DTX:IO = 8 mA
Input Leakage Current
IL
-10
--
10
A
Table 6. DC Characteristics, VDDA = VDDD = 3.3 V
(VDDA,VDDD = 3.13 V to 3.47 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage
Symbol VIH VIL VOH
Test Condition
Min 0.7 VD
"
Typ -- -- --
Max -- 0.3 VD
"
Unit V V V
--
DIO1,DIO2,SDITHRU:IO = - 2 mA SDO, DTX:IO = -4 mA DOUT: IO = -40 mA
VD - 0.6
--
VD - 0.8 --
-- --
-- 0.4
V V
Low Level Output Voltage
VOL
DIO1,DIO2,DOUT,SDITHRU: IO = 2 mA SDO,INT,DTX:IO = 4 mA
Input Leakage Current
IL
-10
--
10
A
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Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Table 7. Power Supply Characteristics
(VDDA,VDDD = 3.13 V to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade)
Parameter Power Supply Current, Analog and Digital
Symbol IA + ID
Test Condition Sleep (RESET = 0) Open Active on-hook ETBO = 4 mA Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA, ILIM = 20 mA Ground-start Ringing Sinewave, REN = 1, VPK = 56 V
Typ1 0.1 33 46
Typ2 0.25 42.8 57
Max 0.42 49 68
Unit mA mA mA
57 73 36 45 -- -- -- -- -- -- --
72 88 47 55 0 0 3 11 30 2 5.5
83 99 55 65 -- -- -- -- -- -- --
mA mA mA mA mA mA mA mA mA mA mA
Power Supply Current, VBAT3
IBAT
Sleep (RESET = 0) Open (DCOF = 1) Active on-hook VOC = 48 V, ETBO = 4 mA Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA, ILIM = 20 mA Ground-start Ringing VPK_RING = 56 VPK, sinewave ringing, REN = 1
Notes: 1. VDDD, VDDA = 3.3 V. 2. VDDD, VDDA = 5.25 V. 3. IBAT = current from VBAT (the large negative supply). For a switched-mode power supply regulator efficiency of 71%, the user can calculate the regulator current consumption as IBAT " VBAT/(0.71 " VDC).
Preliminary Rev. 0.9
13
Si3 21 0/Si3 211/Si321 2
Table 8. Absolute Maximum Ratings
Parameter DC Supply Voltage Input Current, SI3210 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Symbol VD IIN VIND TA TSTG Value -0.5 to 6.0 10 -0.3 to (VD + 0.3) -40 to 100 -40 to 150 Unit V mA V C C
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 9. Switching Characteristics--General Inputs
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade, CL = 20 pF)
Parameter Rise Time, RESET RESET Pulse Width
Symbol tr trl
Min -- 100
Typ -- --
Max 20 --
Unit ns ns
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD - 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
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Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Table 10. Switching Characteristics--SPI Interface
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade, CL = 20 pF
Parameter Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active Delay Time, SCLK Fall to SDO Transition Delay Time, CS Rise to SDO Tri-state Setup Time, CS to SCLK Fall Hold Time, CS to SCLK Rise Setup Time, SDI to SCLK Rise Hold Time, SDI to SCLK Rise Delay Time between Chip Selects
Symbol tc tr tf td1 td2 td3 tsu1 th1 tsu2 th2 tcs
Test Conditions
Min 0.062 -- -- -- -- -- 25 20 25 20 220
Typ -- -- -- -- -- -- -- -- -- -- --
Max -- 25 25 20 20 20 -- -- -- -- --
Unit sec ns ns ns ns ns ns ns ns ns ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD -0.4 V, VIL = 0.4 V
SCLK
CS
t CS
SDI
SDO
Figure 7. SPI Interface Timing Diagram
Preliminary Rev. 0.9
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Si3 21 0/Si3 211/Si321 2
Table 11. Switching Characteristics--PCM Highway Serial Interface
VD = 3.13 to 5.25 V, TA = 0 to 70C for K-Grade, -40 to 85C for B-Grade, CL = 20 pF
Parameter PCLK Frequency
Symbol 1/tc
Test Conditions
Min 1 -- -- -- -- -- -- -- --
Typ 1 0.256 0.512 0.768 1.024 1.536 2.048 4.096 8.192
Max 1 -- -- -- -- -- -- -- --
Units MHz MHz MHz MHz MHz MHz MHz MHz
PCLK Duty Cycle Tolerance PCLK Period Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Delay Time, PCLK Rise to DTX Active Delay Time, PCLK Rise to DTX Transition Delay Time, PCLK Rise to DTX Tri-state 2 Setup Time, FSYNC to PCLK Fall Hold Time, FSYNC to PCLK Fall Setup Time, DRX to PCLK Fall Hold Time, DRX to PCLK Fall
tdty tjitter tr tf td1 td2 td3 tsu1 th1 tsu2 th2
40 120 -- -- -- -- -- 25 20 25 20
50 -- -- -- -- -- -- -- -- -- --
60 120 25 25 20 20 20 -- -- -- --
% ns ns ns ns ns ns ns ns ns ns
Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VI/O -0.4V, VIL = 0.4V 2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
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Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Figure 8. PCM Highway Interface Timing Diagram
Preliminary Rev. 0.9
17
18 Preliminary Rev. 0.9
Si3 21 0/Si3 211/Si321 2
Figure 9. SI3210 Typical Application Circuit Using DC-to-DC Converter
SI3210/Si3211/Si3212
Table 12. SI3210 External Component Values--DC-to-DC Converter
Component C1,C2 C3,C4,C7,C8 C5,C6,C10 C9 C11,C14,C26 C251,C30 R1,R2,R3,R4,R5 R6,R7 R8,R9 R10,R11 R12,R13 R14 R15 R16,R172 R182 R192,R202 R21 D1 L12 Value 10 F, 10 V, Ceramic/Tantalum, 20% 220 nF, 100 V, X7R, 20% 22 nF, 100 V, X7R, 20% 10 F, 100 V, Electrolytic, 20% 0.1 F, 100 V, X7R, 20% 10 F, 16 V, Electrolytic, 20% 200 k, 1/10 W, 1% 80.6 , 1/4 W, 1% 470 , 1/10 W, 1% 10 , 1/10 W, 5% 5.1 k, 1/10 W, 5% 40.2 k, 1/10 W, 1% 243 , 1/10 W, 1% 200 , 1/10 W, 5% 0.33 , 1/4 W, 5% 56.2 k, 1/10 W, 1% 15 , 1/4 W, 1% Ultra Fast Recovery 200 V 1A Rectifier 100 H Shielded Inductor Central Semi CMR1U-02; General Semi ES1D API Delevan SPD127 series, Sumida CDRH127 series, Datatronics DR340-1 series, Coilcraft DS5022, TDK SLF12565 Central Semi CMPT5401; ON Semi MMBT5401LT1, 2N5401; Zetex FMMT5401 Central Semi CZT5551, ON Semi 2N5551 Zetex FZT953, FZT955, ZTX953, ZTX955 ON Semi MMBT2222ALT1, MPS2222A; Central Semi CMPT2222A; Zetex FMMT2222 Supplier/Part Number Murata, Panasonic Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic Murata, Johanson, Novacap, Venkel Panasonic
Q1,Q2,Q3,Q4 Q5,Q6 Q73 Q8
100 V, PNP, BJT 100 V, NPN, BJT 120 V, High Current Switching BJT NPN General Purpose BJT
Notes: 1. Voltage rating of this device must be greater than VDC. 2. Value selection for this component varies according to application specific parameters. 3. For VBAT 60 V contact the factory for other component choices.
Preliminary Rev. 0.9
19
20 Preliminary Rev. 0.9
Si3 21 0/Si3 211/Si321 2
Figure 10. SI3210/11/12 Typical Application Circuit Using External Battery
SI3210/Si3211/Si3212
Table 13. SI3210/11/12 External Component Values--External Battery
Component C1,C2 C3,C4,C7,C8 C5,C6 C9,C10 R1,R2,R3,R4,R5 R6,R7 R8,R9 R10,R11 R12,R13 R14 R15 R16 R18 D1 Q1,Q2,Q3,Q4,Q7 Q5,Q6 Q8 Value 10 F, 10 V, Ceramic/Tantalum, 20% 220 nF, 100 V, X7R, 20% 22 nF, 100 V, X7R, 20% 0.1 F, 100 V, Electrolytic, 20% 200 k, 1/10 W, 1% 80.6 , 1/4 W, 1% 470 , 1/10 W, 1% 10 , 1/10 W, 5% 5.1 k, 1/10 W, 5% 40.2 k, 1/10 W, 1% 243 , 1/10 W, 1% 47 k, 1/10 W, 5% 1.8 k, 1/10 W, 5% 200 V 1A Rectifier 100 V, PNP, BJT 100 V, NPN, BJT 100 V, NPN, BJT ON Semi MRA4003, 1N4003 Central Semi CMPT5401; ON Semi MMBT5401LT1, 2N5401; Zetex FMMT5401 Central Semi CZT5551, ON Semi 2N5551 Central Semi CMPT5551, ON Semi 2N5551 Supplier/Part Number Murata, Panasonic Murata, Johanson, Novacap, Venkel Murata, Johanson, Novacap, Venkel Panasonic
Preliminary Rev. 0.9
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Si3 21 0/Si3 211/Si321 2
Functional Description
The ProSLICTM is a single low-voltage CMOS device that provides all the SLIC, codec, DTMF detection, and signal generation functions needed for a complete analog telephone interface. The ProSLIC performs all battery, overvoltage, ringing, supervision, codec, hybrid, and test (BORSCHT) functions. Unlike most monolithic SLICs, the SI3210 does not require externally supplied high-voltage battery supplies. Instead, it generates all necessary battery voltages from a 5 V to 30 V supply using its own DC-to-DC converter controller. Two fully programmable tone generators can produce DTMF tones, phase continuous FSK (caller ID) signaling, and call progress tones. DTMF decoding and pulse metering signal generation are also integrated. All high-voltage functions are implemented using a few low-cost discrete components as shown in the typical application circuits in Figure 9 and Figure 10. The ProSLIC is ideal for short loop applications, such as terminal adapters, cable telephony, PBX/key systems, wireless local loop (WLL), and voice over IP solutions. The device meets all relevant LSSGR and CCITT standards. The linefeed provides programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission ringing voltage. Loop current and voltage are continuously monitored using an integrated A/D converter. Balanced 5 REN ringing with or without a programmable DC offset is integrated. The available offset, frequency, waveshape, and cadence options are designed to ring the widest variety of terminal devices and to reduce external controller requirements. A complete audio transmit and receive path is integrated, including DTMF decoding, AC impedance, and hybrid gain. These features are software programmable, allowing for a single hardware design to meet international requirements. Digital voice data transfer occurs over a standard PCM bus. Control data is transferred using a standard SPI. The device is available in a 38-pin TSSOP. DC Feed Characteristics The ProSLIC has programmable constant voltage and constant current zones as depicted in Figure 11. Open circuit TIP-to-RING voltage (VOC) defines the constant voltage zone and is programmable from 0 V to 94.5 V in 1.5 V steps. The loop current limit (ILIM) defines the constant current zone and is programmable from 20 mA to 41 mA in 3 mA steps. The ProSLIC has an inherent DC output resistance (RO) of 160 .
V (T IP-RING ) (V) Constant Voltage Zone
VOC
R O =160 ILIM
Constant Current Zone ILO O P (m A)
Figure 11. Simplified DC Current/Voltage Linefeed Characteristic
The TIP-to-RING voltage (VOC) is offset from ground by a programmable voltage (VCM) to provide voltage headroom to the positive-most terminal (TIP in forward polarity states and RING in reverse polarity states) for carrying audio signals. Table 14 summarizes the parameters to be initialized before entering an active state.
Table 14. Programmable Ranges of DC Linefeed Characteristics
Parameter Programmable Range 20 to 41 mA Default Value 20 mA Register Bits ILIM[2:0] Location*
ILIM VOC VCM
Direct Register 71 Direct Register 72 Direct Register 73
Linefeed Interface
The ProSLIC's linefeed interface offers a rich set of features and programmable flexibility to meet the broadest applications requirements. The DC linefeed characteristics are software programmable; key current, voltage, and power measurements are acquired in realtime and provided in software registers.
0 to 94.5 V
48 V
VOC[5:0]
0 to 94.5 V
3V
VCM[5:0]
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly.
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Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses low-cost external components to control the high voltages required for subscriber line interfaces. Figure 12 is a simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. The ProSLIC uses both voltage and current sensing to control TIP and RING. DC and AC line voltages on TIP and RING are measured through sense resistors RDC and RAC, respectively. The ProSLIC uses linefeed transistors QP and QN to drive TIP and RING. QDN isolates the high-voltage base of QN from the ProSLIC. The ProSLIC measures voltage at various nodes in order to monitor the linefeed current. RDC, RSE, and RBAT provide access to these measuring points. The sense circuitry is calibrated on-chip to guarantee measurement accuracy with standard external component tolerances. See "Linefeed Calibration" on page 28 for details. Linefeed Operation States The ProSLIC linefeed has eight states of operation as shown in Table 15. The state of operation is controlled using the Linefeed Control register (direct Register 64). The open state turns off all currents into the external bipolar transistors and can be used in the presence of fault conditions on the line and to generate Open Switch Intervals (OSIs). TIP and RING are effectively tri-stated with a DC output impedance of about 150 k. The ProSLIC can also automatically enter the open state if it detects excessive power being consumed in the external bipolar transistors. See "Power Monitoring and Line Fault Detection" on page 25 for more details. In the forward active and reverse active states, linefeed circuitry is on and the audio signal paths are powered down. In the forward and reverse on-hook transmission states audio signal paths are powered up to provide data transmission during an on-hook loop condition. The TIP Open state turns off all control currents to the external bipolar devices connected to TIP and provides an active linefeed on RING for ground start operation. The RING Open state provides similar operation with the RING drivers off and TIP active. The ringing state drives waveforms onto the line. programmable ringing Loop Voltage and Current Monitoring The ProSLIC continuously monitors the TIP and RING voltages and external BJT currents. These values are available in registers 78-89. Table 16 on page 25 lists the values that are measured and their associated registers. An internal A/D converter samples the measured voltages and currents from the analog sense circuitry and translates them into the digital domain. The A/D updates the samples at an 800 Hz rate. Two derived values are also reported--loop voltage and loop current. The loop voltage, VTIP - VRING, is reported as a 1-bit sign, 6-bit magnitude format. For ground start operation the reported value is the RING voltage. The loop current, (IQ1 - IQ2 + IQ5 -IQ6)/2, is reported in a 1bit sign, 6-bit magnitude format. In RING open and TIP open states the loop current is reported as (IQ1 - IQ2) + (IQ5 -IQ6).
Preliminary Rev. 0.9
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Au d io C od ec A/D
M o nito r A/D A/D
DSP
D /A D /A S LIC D AC
B attery Sen se
On-Chip
AC C o n tro l
AC S ense
DC C o n tro l
D C S en se
E m itter S en se
External Components
RAC C AC
AC C o n tro l Loop
QP R BP
Q DN
DC C o n tro l Loop
RDC
RSE
RBAT
T IP o r R IN G
QN
RE VBAT
Figure 12. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 15. ProSLIC Linefeed Operations
LF[2:0]* 000 001 010 011 100 101 110 111 Linefeed State Open Forward Active Forward On-Hook Transmission TIP Open Ringing Reverse Active Reverse On-Hook Transmission Ring Open Description TIP and RING tri-stated. VTIP > VRING. VTIP > VRING; audio signal paths powered on. TIP tri-stated, RING active; used for ground start. Ringing waveform applied to TIP and RING. VRING > VTIP. VRING > VTIP; audio signal paths powered on. RING tri-stated, TIP active.
Note: The Linefeed register (LF) is located in direct Register 64.
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Table 16. Measured Realtime Linefeed Interface Characteristics
Parameter Loop Voltage Sense (VTIP - VRING) Loop Current Sense Measurement Range -94.5 to +94.5 V Resolution 1.5 V Register Bits LVSP, LVS[6:0] LCSP, LCS[5:0] VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0] Location* Direct Register 78
-78.75 to +78.5 mA
1.25 mA
Direct Register 79
TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 (VBAT) Battery Voltage Sense 2 (VBAT) Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense
0 to -95.625 V 0 to -95.625 V 0 to -95.625 V 0 to -95.625 V 0 to 79.7 mA 0 to 79.7 mA 0 to 9.45 mA 0 to 9.45 mA 0 to 79.7 mA 0 to 79.7 mA
0.375 V 0.375 V 0.375 V 0.375 V 0.31 mA 0.31 mA 0.037 mA 0.037 mA 0.31 mA 0.31 mA
Direct Register 80 Direct Register 81 Direct Register 82 Direct Register 83 Direct Register 84 Direct Register 85 Direct Register 86 Direct Register 87 Direct Register 88 Direct Register 89
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly.
Power Monitoring and Line Fault Detection In addition to reporting voltages and currents, the ProSLIC continuously monitors the power dissipated in each external bipolar transistor. Realtime output power of any one of the six linefeed transistors can be read by setting the Power Monitor Pointer (direct Register 76) to point to the desired transistor and then reading the Line Power Output Monitor (direct Register 77). The realtime power measurements are low-pass filtered and compared to a maximum power threshold. Maximum power thresholds and filter time constants are software programmable and should be set for each transistor pair based on the characteristics of the transistors used. Table 17 describes the registers associated with this function. If the power in any external transistor exceeds the programmed threshold, a power alarm event is triggered. The ProSLIC sets the Power Alarm register bit, generates an interrupt (if enabled), and automatically enters the Open state (if
AOPN = 1). This feature protects the external transistors from fault conditions and, combined with the loop voltage and current monitors, allows diagnosis of the type of fault condition present on the line. The value of each thermal low-pass filter pole is set according to the equation:
4096 thermal LPF register = ---------------800
where is the thermal time constant of the transistor package, 4096 is the full range of the 12-bit register, and 800 is the sample rate in hertz. Generally = 3 seconds for SOT223 packages and = 0.16 seconds for SOT23, but check with the manufacturer for the package thermal constant of a specific device. For example, the power alarm threshold and low-pass filter values for Q1 & Q2 using a SOT23 package transistor are computed as follows:
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210 mW PPT12 [ 7:0 ] = 210 mW = 256 ------------------------- = 9 6000 mW
Thus, indirect Register 32 should be set to 9 27 = 1152 = 0480h since PPT12 is shifted by 7 bits in the register space.
"
so indirect Register 37 should be set to 32 23 = 256 = 0100h since NQ12 is shifted by 3 bits in the register space.
"
Note: The power monitor resolution for Q3 and Q4 is different from that of Q1, Q2, Q5, and Q6.
NQ12[12:0] = 4096/(800 Hz 0.16 s) = 32,
"
Table 17. Associated Power Monitoring and Power Fault Registers
Parameter Description/ Range 0 to 5 points to Q1 to Q6, respectively 0 to 6 W for Q1, Q2, Q5, Q6 0 to 0.7W for Q3, Q4 0 to 6 W 0 to 0.7 W 0 to 6 W Resolution Register Bits PWRMP[2:0] Location*
Power Monitor Pointer
n/a
Direct Register 76
Line Power Monitor Output
23.4 mW 2.76 mW
PWROM[7:0]
Direct Register 77
Power Alarm Threshold, Q1 & Q2 Power Alarm Threshold, Q3 & Q4 Power Alarm Threshold, Q5 & Q6 Thermal LPF Pole, Q1 & Q2 Thermal LPF Pole, Q3 & Q4 Thermal LPF Pole, Q5 & Q6 Power Alarm Interrupt Pending
23.4 mW 2.76 mW 23.4 mW
PPT12[7:0] PPT34[7:0] PPT56[7:0] NQ12[7:0] NQ34[7:0] NQ56[7:0]
Indirect Register 32 Indirect Register 33 Indirect Register 34 Indirect Register 37 Indirect Register 38 Indirect Register 39 Direct Register 19
see equation above see equation above see equation above Bits 2 to 7 correspond to Q1 to Q6, respectively Bits 2 to 7 correspond to Q1 to Q6, respectively 0 = manual mode 1 = enter open state upon power alarm n/a
QnAP[n+1], where n =1 to 6 QnAE[n+1], where n = 1 to 6 AOPN
Power Alarm Interrupt Enable
n/a
Direct Register 22
Power Alarm Automatic/Manual Detect
n/a
Direct Register 67
*Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
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LCS L VS In put S ignal P rocessor IS P _O U T D igital LP F + D ebounce Filter - N C LR LFS LC V E H YS TE N Loop C losure Threshold LC D I LC IE
LC R
Interrupt Logic
LC IP
LC R T L C R TL
Figure 13. Loop Closure Detection
Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during on-hook transmission or onhook active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter. The functional blocks required to implement loop closure detection are shown in Figure 13. The primary input to the system is the Loop Current Sense value provided in the LCS register (direct Register 79). The LCS value is processed in the Input Signal Processor when the ProSLIC is in the on-hook transmission or on-hook active linefeed state, as indicated by the Linefeed Shadow register, LFS[2:0] (direct Register 64). The data then feeds into a programmable digital low-pass filter, which removes unwanted AC signal components before threshold detection. The output of the low-pass filter is compared to a programmable threshold, LCRT (indirect register 28). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the loop closure debounce interval, LCDI (direct Register 69). If the debounce interval has been satisfied, the LCR bit will be set to indicate that a valid loop closure has occurred. A loop closure interrupt is generated if enabled by the LCIE bit (direct Register 22). Table 18 lists the registers that must be written or monitored to correctly detect a loop closure condition. Loop Closure Threshold Hysteresis Silicon revisions C and higher support the addition of programmable hysteresis to the loop closure threshold, which can be enabled by setting HYSTEN = 1 (direct Register 108, bit 0). The hysteresis is defined by LCRT (indirect Register 28) and LCRTL (indirect Register 43), which set the upper and lower bounds, respectively. Voltage-Based Loop Closure Detection Silicon revisions C and higher also support an optional voltage-based loop closure detection mode, which is enabled by setting LCVE = 1 (direct Register 108, bit 2). In this mode the loop voltage is compared to the loop closure threshold register (LCRT) which represents a minimum voltage threshold instead of a maximum current threshold. If hysteresis is also enabled, then LCRT represents the upper voltage boundary and LCRTL represents the lower voltage boundary for hysteresis. Although voltage-based loop closure detection is an option, the default current-based loop closure detection is recommended.
Table 18. Register Set for Loop Closure Detection
Parameter Register Location Loop Closure LCIP Direct Reg. 19 Interrupt Pending Loop Closure LCIE Direct Reg. 22 Interrupt Enable Loop Closure Threshold LCRT[5:0] Indirect Reg. 28 Loop Closure LCRTL[5:0] Indirect Reg. 43 Threshold--Lower Loop Closure Filter NCLR[12:0] Indirect Reg. 35 Coefficient Loop Closure Detect LCR Direct Reg. 68 Status (monitor only) Loop Closure Detect LCDI[6:0] Direct Reg. 69 Debounce Interval Hysteresis Enable HYSTEN Direct Reg. 108 Voltage-Based Loop LCVE Direct Reg. 108 Closure
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Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset. It is recommended that a calibration be executed following system power-up. Upon release of the chip reset, the SI3210 will be in the open state. After powering up the DC-to-DC converter and allowing it to settle for time (tsettle) the calibration can be initiated. Additional calibrations may be performed, but only one calibration should be necessary as long as the system remains powered up. During calibration, VBAT, VTIP, and VRING voltages are controlled by the calibration engine to provide the correct external voltage conditions for the algorithm. Calibration should be performed in the on-hook state. RING or TIP must not be connected to ground during the calibration. minimum required for any given mode of operation. DC-to-DC Converter Architecture (SI3210 Only) The control logic for a pulse width modulated (PWM) DC-to-DC converter is incorporated in the SI3210. The external support circuitry needed is shown in Figure 14. Output pins, DCDRV and DCFF, are used to switch the bipolar transistors QBAT and QBATD. QBATD is used to turn on and off QBAT by controlling the base current. The capacitor CFF is used to provide instantaneous current for turning off QBAT, which enhances efficiency. The polarity of DCFF is opposite to that of DCDRV. Although not recommended when using the application circuit in Figure 14, the polarity of DCFF can be inverted using the DCPOL bit of the DC-to-DC Converter Switching Delay register (direct Register 93, bit 5). The DC-to-DC converter circuit is powered on when the DCOF bit in the Power Down Register (direct Register 14, bit 4) is cleared to 0. The switching regulator circuit within the SI3210 is a high performance, pulse-width modulation controller. The control pins are driven by the PWM controller logic in the SI3210. The regulated output voltage (VBAT) is sensed by the SVBAT pin and is used to detect whether the output voltage is above or below an internal reference for the desired battery voltage. The DC monitor pins SDCH and SDCL monitor input current and voltage to the DC-to-DC converter external circuitry. If an overload condition is detected, the PWM controller will turn off QBAT for the remainder of a PWM period to prevent damage to external components. The PWM controller operates at a frequency set by the DC-to-DC Converter PWM register (direct Register 92). During a PWM period the outputs of the control pins DCDRV and DCFF are asserted for a time given by the read-only PWM Pulse Width register (direct Register 94). The DC-to-DC converter must be off for some time in each cycle to allow the inductor, L1, to transfer its stored energy to the output capacitor, C9. This minimum off time can be set through the DC-to-DC Converter Switching Delay register, (direct Register 93). The number of 16.384 MHz clock cycles that the controller is off is equal to DCTOF (bits 0 through 4) plus 4. If the DC Monitor pins detect an overload condition, the DC-to-DC converter interrupts its conversion cycles regardless of the register settings to prevent component damage. These inputs should be calibrated by writing the DCCAL bit (bit 7) of the DC-to-DC Converter Switching Delay register, direct Register 93, after the DC-to-DC converter has been turned on. Because the SI3210 dynamically regulates its own battery supply voltage using the DC-to-DC converter
Battery Voltage Generation and Switching
The SI3210 supports two modes of battery supply operation. First, the SI3210 integrates a DC-to-DC converter controller that dynamically regulates a single output voltage. This mode eliminates the need to supply large external battery voltages. Instead, it converts a single positive input voltage (5 to 30 V DC) into the realtime battery voltage needed for any given state according to programmed linefeed parameters. Second, the SI3210 supports switching between high and low battery voltage supplies, as would a traditional monolithic bipolar SLIC. Other ProSLIC family members, the Si3211 and Si3212, support only this second mode of battery supply operation. For single to low channel count applications, the SI3210 proves to be an economical choice, as the DC-to-DC converter eliminates the need to design and build highvoltage power supplies. For higher channel count applications where centralized battery voltage supply is economical, or for modular legacy systems where battery voltage is already available, the Si3211 and Si3212 are recommended. DC-to-DC Converter General Description (SI3210 Only) The DC-to-DC converter dynamically generates the large negative voltages required to operate the linefeed interface. The SI3210 acts as the controller for a buckboost DC-to-DC converter that converts 5 to 30 V DC to the desired negative battery voltage. In addition to eliminating external power supplies, this allows the SI3210 to dynamically control the battery voltage to the
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controller, the battery voltage (VBAT) is offset from the negative-most terminal by a programmable voltage (VOV) to allow voltage headroom for carrying audio signals. As mentioned before, the SI3210 dynamically adjusts VBAT to suit the particular circuit requirement. To
+ V DC
illustrate this, the behavior of VBAT in the active state is shown in Figure 15. In the active state, the TIP-to-RING open circuit voltage is kept at VOC in the constant voltage region while the regulator output voltage, VBAT = VCM + VOC + VOV.
R19 56.2 k RM ON H DC M O NH R16 200 RS W R18
0 .33
C25 10 F
C14 0.1 F
R20 56.2 k RM ON L DC M O NL C10 22 nF CFF
RV DC
Q7 FZT953 Q BAT Q8 2222 Q BATD D1 R21 15 RFILT
DC FF
VBAT
DC DR V
R17 200 RS W E 5%
L1 100 H LSW
C9 10 F CB AT
C11 0.1 F
C26 0.1 F CFILT
Figure 14. Typical DC-to-DC Converter Application Circuit
VOC
C o nstan t I R egio n
I L IM V CM
C o nstan t V R eg ion
R LOOP
V T IP
TR
V BATL
AC
K=
0
|V TIP - V R IN G |
VOC
T R AC K =1 VOV V R IN G VOV V BAT V
Figure 15. VTIP, VRING, and VBAT in the Forward Active State
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Table 19. Associated Relevant DC-to-DC Converter Registers
Parameter DC-to-DC Converter Power-off Control DC-to-DC Converter Calibration Enable/Status DC-to-DC Converter DCFF pin Polarity DC-to-DC Converter PWM Period DC-to-DC Converter Min. Off Time High Battery Voltage--VBATH Low Battery Voltage--VBATL Battery Mode VOV Range n/a n/a n/a 0 to 15.564 us (0 to 1.892 us) + 4 ns 0 to -94.5 V 0 to -94.5 V n/a 0 to -9 V or 0 to -13.5 V Resolution n/a n/a n/a 61.035 ns 61.035 ns 1.5 V 1.5 V n/a 1.5 V Register Bit DCOF DCCAL DCPOL DCN[7:0] DCTOF[4:0] VBATH[5:0] VBATL[5:0] EXTBAT VMIND[3:0] VOV Location Direct Register 14 Direct Register 93 Direct Register 93 Direct Register 92 Direct Register 93 Direct Register 74 Direct Register 75 Direct Register 66 Indirect Register 41 Direct Register 66
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
When the loop current attempts to exceed ILIM, the DC line driver circuit enters constant current mode allowing the TIP to RING voltage to track RLOOP. As the TIP terminal is kept at a constant voltage, it is the RING terminal voltage that tracks RLOOP and, as a result, the |VBAT| voltage will also track RLOOP. In this state, |VBAT| = ILIM RLOOP + VCM +VOV. As RLOOP decreases below the VOC/ILIM mark, the regulator output voltage can continue to track RLOOP (TRACK = 1), or the RLOOP tracking mechanism is stopped when |VBAT| = |VBATL| (TRACK = 0). The former case is the more common application and provides the maximum power dissipation savings. In principle, the regulator output voltage can go as low as |VBAT| = VCM+ VOV, offering significant power savings.
"
terminal equipment on the same line. TRACK = 0 mode is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds) and cannot change rapidly for TRACK = 1 mode. Therefore, the brief on-hook voltage measurement would yield approximately the same voltage as the off-hook line voltage and would cause the terminal equipment to incorrectly sense another offhook terminal. DC-to-DC Converter Enhancements Silicon revisions C and higher support two enhancements to the DC-to-DC converter. The first is a multi-threshold error control algorithm that enables the DC-to-DC converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5). The second enhancement is an audio band filter that removes audio band noise from the DC-to-DC converter control loop. This option is enabled by setting DCFIL = 1 (direct Register 108, bit 1). DC-to-DC Converter During Ringing When the ProSLIC enters the ringing state, it requires voltages well above those used in the active mode. The voltage to be generated and regulated by the DC-to-DC
When TRACK = 0, |VBAT| will not decrease below VBATL. The RING terminal voltage, however, continues to decrease with decreasing RLOOP. The power dissipation on the NPN bipolar transistor driving the RING terminal can become large and may require a higher power rating device. The non-tracking mode of operation is required by specific terminal equipment which, in order to initiate certain data transmission modes, goes briefly on-hook to measure the line voltage to determine whether there is any other off-hook
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converter during a ringing burst is set using the VBATH register (direct Register 74). VBATH can be set between 0 and -94.5 V in 1.5 V steps. To avoid clipping the ringing signal, VBATH must be set larger than the ringing amplitude. At the end of each ringing burst the DC-toDC converter adjusts back to active state regulation as described above. External Battery Switching The ProSLIC will operate in the external battery mode when EXTBAT = 1 (direct Register 66). For the Si3211 and Si3212 devices, EXTBAT is permanently set to 1 because the DC-to-DC converter is not available for these devices. For the SI3210, the on-chip DC-to-DC converter circuit is disabled, and the device requires one or two external battery voltage supplies. Typically a high voltage battery (e.g., -70 V) is used for on-hook and ringing states, and a low voltage battery (e.g., -24 V) is used for the off-hook condition. The ProSLIC uses an external transistor to switch between the two supplies. (See Figure 16.) When the ProSLIC changes operating states, it automatically switches battery supplies if the automatic/ manual control bit ABAT (direct Register 67, bit 3) is set. For example, the ProSLIC will switch from high battery to low battery when it detects an off-hook event through either a ring trip or loop closure event. If automatic battery selection is disabled (ABAT = 0), the battery is selected by the Battery Feed Select bit, BATSL (direct Register 66, bit 1). Silicon revisions C and higher support the option to add a 60 ms debounce period to the battery switching circuit when transitioning from high battery to low battery. This option is enabled by setting SWDB = 1 (direct Register 108, bit 3). This debounce minimizes battery transitions in the case of pulse dialing or other quick onhook to off-hook transitions.
R18
Si3211/12
DCSW
Q7
R17 D1 C9
V REG
V BATL
Q8 R16 C10
V BATH
Figure 16. Circuit Solution for Battery Switching
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Tone Generation
Two digital tone generators are provided in the ProSLIC. They allow the generation of a wide variety of single or dual tone frequency and amplitude combinations and spare the user the effort of generating the required POTS signaling tones on the PCM highway. DTMF, FSK (caller ID), call progress, and other tones can all be generated on-chip. The tones can be sent to either the receive or transmit paths (see Figure 22 on page 41).
8 kHz Clock OnE
Z ero C ros s L og ic
Tone Generator Architecture A simplified diagram of the tone generator architecture is shown in Figure 17. The oscillator, active/inactive timers, interrupt block, and signal routing block are connected to give the user flexibility in creating audio signals. Control and status register bits are placed in the figure to indicate their association with the tone generator architecture. These registers are described in more detail in Table 20.
OZn Zero Cross OSSn
E nable
8 kHz Clock to TX Path
16-Bit Modulo Counter
O AT E xpire O IT E xpire
Load Logic
Two-Pole Resonance R egister Oscillator
Load
Signal Routing
to RX Path
OATn OATnE OITn OITnE INT Logic INT Logic OnIP REL*
OSCn OnSO OnIE OnAP OSCnY OSCnX
OnAE *Tone Generator 1 Only n = "1" or "2" for Tone Generator 1 and 2, respectively
Figure 17. Simplified Tone Generator Diagram
Oscillator Frequency and Amplitude Each of the two tone generators contains a two-pole resonate oscillator circuit with a programmable frequency and amplitude, which are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two oscillators is 8000 Hz. The equations are as follows: coeffn = cos(2 fn/8000 Hz), where fn is the frequency to be generated; OSCn = coeffn (215);
"
2852 coeff 1 = cos ---------------- = 0.78434 8000 OSC1 = 0.78434 ( 2 ) = 25701 = 6465h OSC1X =
14 15 0.21556 -------------------- ( 2 - 1 ) 0.5 = 1424 = 590h 1.78434 15
OSC1Y = 0
21336 coeff 2 = cos ------------------- = 0.49819 8000
OSCnX =
14
Desired V RMS 15 1 - coeff ----------------------- ( 2 - 1 ) --------------------------------------1.11 VRMS 1 + coeff
OSC2 = 0.49819 (215) = 16324 = 3FC4h
OSC2X =
14 15 0.50181 -------------------- ( 2 - 1 ) 0.5 = 2370 = 942h 1.49819
where desired Vrms is the amplitude to be generated; OSCnY = 0, n = 1 or 2 for oscillator 1 or oscillator 2, respectively. For example, in order to generate a DTMF digit of 8, the two required tones are 852 Hz and 1336 Hz. Assuming the generation of half-scale values (ignoring twist) is desired, the following values are calculated:
OSC2Y = 0 The computed values above would be written to the corresponding registers to initialize the oscillators. Once the oscillators are initialized, the oscillator control registers can be accessed to enable the oscillators and direct their outputs.
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Tone Generator Cadence Programming Each of the two tone generators contains two timers, one for setting the active period and one for setting the inactive period. The oscillator signal is generated during the active period and suspended during the inactive period. Both the active and inactive periods can be programmed from 0 to 8 seconds in 125 s steps. The active period time interval is set using OAT1 (direct registers 36 and 37) for tone generator 1 and OAT2 (direct registers 40 and 41) for tone generator 2. To enable automatic cadence for tone generator 1, define the OAT1 and OIT1 registers and then set the O1TAE bit (direct Register 32, bit 4) and O1TIE bit (direct Register 32, bit 3). This enables each of the timers to control the state of the Oscillator Enable bit, O1E (direct Register 32, bit 2). The 16-bit counter will begin counting until the active timer expires, at which time the 16-bit counter will reset to zero and begin counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures that each oscillator pulse ends without a DC component. The timing diagram in Figure 18 is an example of an output cadence using the zero crossing feature. One-shot oscillation can be achieved by enabling O1E and O1TAE. Direct control over the cadence can be achieved by controlling the O1E bit (direct Register 32, bit 2) directly if O1TAE and O1TIE are disabled. The operation of tone generator 2 is identical to that of tone generator 1 using its respective control registers.
Note: Tone Generator 2 should not be enabled simultaneously with the ringing oscillator due to resource sharing within the hardware.
Continuous phase frequency-shift keying (FSK) waveforms may be created using tone generator 1 (not available on tone generator 2) by setting the REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer (OAT1).
Table 20. Associated Tone Generator Registers
Tone Generator 1 Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Description / Range Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 sec 0 to 8 sec Status and control registers Tone Generator 2 Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 initial phase coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer Oscillator 2 Control Description / Range Sets oscillator frequency Sets oscillator amplitude Sets initial phase 0 to 8 sec 0 to 8 sec Status and control registers Register OSC2[15:0] OSC2X[15:0] OSC2Y[15:0] OAT2[15:0] OIT2[15:0] OSS2, OZ2, O2TAE, O2TIE, O2E, O2SO[1:0] Location Indirect Register 16 Indirect Register 17 Indirect Register 18 Direct Registers 40 & 41 Direct Register 42 & 43 Direct Register 33 Register Bits OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OAT1[15:0] OIT1[15:0] OSS1, REL, OZ1, O1TAE, O1TIE, O1E, O1SO[1:0] Location Indirect Register 13 Indirect Register 14 Indirect Register 15 Direct Registers 36 & 37 Direct Register 38 & 39 Direct Register 32
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O1E
0,1 ...
..., OAT1 0,1 ...
..., OIT1 0,1 ...
..., OAT1 0,1 ...
... ...
OSS1
Tone Gen. 1 Signal Output
Figure 18. Tone Generator Timing Diagram
Enhanced FSK Waveform Generation Silicon revisions C and higher support enhanced FSK generation capabilities, which can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect registers 99-104. The user need only indicate 0-to-1 and 1-to-0 transitions in the information stream. By writing to FSKDAT (direct Register 52), this mode applies a 24 kHz sample rate to tone generator 1 to give additional resolution to timers and frequency generation. Application Note 32 gives detailed instructions on how to implement FSK in this mode. Additionally, sample source code is available from Silicon Laboratories upon request. Tone Generator Interrupts Both the active and inactive timers can generate their own interrupt to signal "on/off" transitions to the software. The timer interrupts for tone generator 1 can be individually enabled by setting the O1AE and O1IE bits (direct Register 21, bits 0 and 1, respectively). Timer interrupts for tone generator two are O2AE and O2IE (direct Register 21, bits 2 and 3, respectively). A pending interrupt for each of the timers is determined by reading the O1AP, O1IP, O2AP, and O2IP bits in the Interrupt Status 1 register (direct Register 18, bits 0 through 3, respectively). ringing cadence. Both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable. Ringing signals of up to 88 V peak or more can be generated, enabling the ProSLIC to drive a 5 REN (1380 + 40 F) ringer load across loop lengths of 2000 feet (160 ) or more. Ringing Architecture The ringing generator architecture is nearly identical to that of the tone generator. The sinusoid ringing waveform is generated using an internal two-pole resonance oscillator circuit with programmable frequency and amplitude. However, since ringing frequencies are very low compared to the audio band signaling frequencies, the ringing waveform is generated at a 1 kHz rate instead of 8 kHz. The ringing generator has two timers that function the same as for the tone generator timers. They allow on/off cadence settings up to 8 sec on/ 8 sec off. In addition to controlling ringing cadence, these timers control the transition into and out of the ringing state. Table 21 summarizes the list of registers used for ringing generation.
Note: Tone generator 2 should not be enabled concurrently with the ringing generator due to resource sharing within the hardware.
Ringing Generation
The ProSLIC provides fully programmable internal balanced ringing with or without a DC offset to ring a wide variety of terminal devices. All parameters associated with ringing are software programmable: ringing frequency, waveform, amplitude, DC offset, and
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Table 21. Registers for Ringing Generation
Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage Ringing DC voltage offset Ringing frequency Ringing amplitude Ringing initial phase Range/ Description Sine/Trapezoid Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled Enabled/ Disabled 0 to 8 sec 0 to 8 sec Ringing State = 100b 0 to -94.5 V 0 to 94.5 V 15 to 100 Hz 0 to 94.5 V Sets initial phase for sinewave and period for trapezoid 0 to 22.5 V Register Bits TSWS RVO RTAE RTIE ROE RAT[15:0] RIT[15:0] LF[2:0] VBATH[5:0] ROFF[15:0] RCO[15:0] RNGX[15:0] RNGY[15:0] Location Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Register 34 Direct Registers 48 and 49 Direct Registers 50 and 51 Direct Register 64 Direct Register 74 Indirect Register 19 Indirect Register 20 Indirect Register 21 Indirect Register 22
Common Mode Bias Adjust During Ringing
VCMR[3:0]
Indirect Register 40
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
When the ringing state is invoked by writing LF[2:0] = 100 (direct Register 64), the ProSLIC will go into the ringing state and start the first ring. At the expiration of RAT, the ProSLIC will turn off the ringing waveform and will go to the on-hook transmission state. At the expiration of RIT, ringing will again be initiated. This process will continue as long as the two timers are enabled and the Linefeed Control register is set to the ringing state. Sinusoidal Ringing To configure the ProSLIC for sinusoidal ringing, the frequency and amplitude are initialized by writing to the following indirect registers: RCO, RNGX, and RNGY. The equations for RCO, RNGX, RNGY are as follows:
RCO = coeff ( 2 )
15
) 1 1 - coeff 15 Desired V PK ( 0 to 94.5 V RNGX = -- ----------------------- 2 ----------------------------------------------------------------------4 1 + coeff 96 V RNGY = 0
In selecting a ringing amplitude, the peak TIP-to-RING ringing voltage must be greater than the selected onhook line voltage setting (VOC, direct Register 72). For example, to generate a 70 VPK 20 Hz ringing signal, the equations are as follows:
2 20 coeff = cos ---------------------- = 0.99211 1000 Hz RCO = 0.99211 ( 2 ) = 32509 = 7EFDh 1 - -------------------- 15 70 RNGX = -- 0.00789 2 ----- = 376 = 0177h 96 4 1.99211 RNGY = 0
15
where
2f coeff = cos ---------------------- 1000 Hz
and f = desired ringing frequency in hertz.
In addition, the user must select the sinusoidal ringing waveform by writing TSWS = 0 (direct Register 34, bit 0).
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Trapezoidal Ringing In addition to the sinusoidal ringing waveform, the ProSLIC supports trapezoidal ringing. Figure 19 illustrates a trapezoidal ringing waveform with offset VROFF. (20 Hz), the rise time requirement is 0.0153 sec.
RCO ( 20 Hz, 1.3 crest factor ) 2 24235 = ----------------------------------- = 396 = 018Ch 0.0153 8000
VTIP-RING
In addition, the user must select the trapezoidal ringing waveform by writing TSWS = 1 in direct Register 34. Ringing DC voltage Offset A DC offset can be added to the AC ringing waveform by defining the offset voltage in ROFF (indirect Register 19). The offset, VROFF, is added to the ringing signal when RVO is set to 1 (direct Register 34, bit 1). The value of ROFF is calculated as follows:
V ROFF 15 ROFF = ----------------- 2 96
VROFF T=1/freq tRISE time
Linefeed Considerations During Ringing
Figure 19. Trapezoidal Ringing Waveform
To configure the ProSLIC for trapezoidal ringing, the user should follow the same basic procedure as in the Sinusoidal Ringing section, but using the following equations:
1 RNGY = -- Period 8000 2 Desired V PK 15 RNGX = ----------------------------------- ( 2 ) 96 V 2 RNGX RCO = -----------------------------tRISE 8000
Care must be taken to keep the generated ringing signal within the ringing voltage rails (GNDA and VBAT) to maintains proper biasing of the external bipolar transistors. If the ringing signal nears the rails, a distorted ringing signal and excessive power dissipation in the external transistors will result. To prevent this invalid operation, set the VBATH value (direct Register 74) to a value higher than the maximum peak ringing voltage. The discussion below outlines the considerations and equations that govern the selection of the VBATH setting for a particular desired peak ringing voltage. First, the required amount of ringing overhead voltage, VOVR, is calculated based on the maximum value of current through the load, ILOAD,PK, the minimum current gain of Q5 and Q6, and a reasonable voltage required to keep Q5 and Q6 out of saturation. For ringing signals up to VPK = 87 V, VOVR = 7.5 V is a safe value. However, to determine VOVR for a specific case, use the equations below.
V AC,PK N REN I LOAD,PK = ------------------ + I OS = VAC,PK ----------------- + I OS RLOAD 6.9 k
RCO is a value which is added or subtracted from the waveform to ramp the signal up or down in a linear fashion. This value is a function of rise time, period, and amplitude, where rise time and period are related through the following equation for the crest factor of a trapezoidal waveform.
3 1t RISE = -- T 1 - ---------- 2 4 CF
where: NREN is the ringing REN load (max value = 5), IOS is the offset current flowing in the line driver circuit (max value = 2 mA), and VAC,PK = amplitude of the AC ringing waveform. It is good practice to provide a buffer of a few more milliamperes for ILOAD,PK to account for possible line leakages, etc. The total ILOAD,PK current should be smaller than 80 mA.
where T = ringing period, and CF = desired crest factor. For example, to generate a 71 VPK, 20 Hz ringing signal, the equations are as follows:
1 1 RNGY ( 20 Hz ) = -- --------------- 8000 = 200 = C8h 2 20 Hz 71 15 RNGX ( 71 VPK ) = ----- 2 = 24235 = 5EABh 96
For a crest factor of 1.3 and a period of 0.05 sec
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+1 V OVR = I LOAD,PK = ------------ 80.6 + 1 V
where is the minimum expected current gain of transistors Q5 and Q6. The minimum value for VBATH is therefore given by the following:
VBATH = V AC,PK + V ROFF + VOVR
Silicon revisions C and higher support the option to briefly increase the maximum differential current limit between the voltage transition of TIP and RING from ringing to a DC linefeed state. This mode is enabled by setting ILIMEN = 1 (direct Register 108, bit 7). Ring Trip Detection A ring trip event signals that the terminal equipment has gone off-hook during the ringing state. The ProSLIC performs ring trip detection digitally using its on-chip monitor A/D converter. The functional blocks required to implement ring trip detection is shown in Figure 20. The primary input to the system is the Loop Current Sense value provided by the current monitoring circuitry and reported in direct Register 79. LCS data is processed by the input signal processor when the ProSLIC is in the ringing state as indicated by the Linefeed Shadow register (direct Register 64). The data then feeds into a programmable digital low pass filter, which removes unwanted AC signal components before threshold detection.
The ProSLIC is designed to create a fully balanced ringing waveform, meaning that the TIP and RING common mode voltage, (VTIP + VRING)/2, is fixed. This voltage is referred to as VCM_RING and is automatically set to the following:
VBATH - VCMR VCM_RING = --------------------------------------------2
VCMR is an indirect register which provides the headroom by the ringing waveform with respect to the VBATH rail. The value is set as a 4-bit setting in indirect Register 40 with an LSB voltage of 1.5 V/LSB.
LCS
In pu t S ig na l P ro c ess o r
IS P _O U T
D ig ital LPF
+
D B IR AW
D eb o u nc e F ilte r
R TP
In terru p t L o g ic
R TIP
- NRTP LFS R in g T rip T h res h o ld R TD I R TIE
RPTP
Figure 20. Ring Trip Detector
The output of the low pass filter is compared to a programmable threshold, RPTP (indirect Register 29). The threshold comparator output feeds a programmable debouncing filter. The output of the debouncing filter remains in its present state unless the input remains in the opposite state for the entire period of time programmed by the ring trip debounce interval, RTDI[6:0] (direct Register 70). If the debounce interval has been satisfied, the RTP bit of direct Register 68 will be set to indicate that a valid ring trip has occurred. A ring trip interrupt is generated if enabled by the RTIE bit (direct Register 22). Table 22 lists the registers that must be written or monitored to correctly detect a ring trip condition. The recommended values for RPTP, NRTP, and RTDI vary according to the programmed ringing frequency. Register values for various ringing frequencies are given in Table 23.
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Table 22. Associated Registers for Ring Trip Detection
Parameter Ring Trip Interrupt Pending Ring Trip Interrupt Enable Ring Trip Threshold Ring Trip Filter Coefficient Ring Trip Detect Status (monitor only) Register RTIP RTIE RPTP[5:0] NRTP[12:0] RTP Location Direct Register 19 Direct Register 22 Indirect Register 29 Indirect Register 36 Direct Register 68
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
Table 23. Recommended Ring Trip Values for Ringing
Ringing Frequency Hz 16.667 20 30 40 50 60 decimal 64 100 112 128 213 256 NRTP hex 0200 0320 0380 0400 06A8 0800 decimal 34 mA 34 mA 34 mA 34 mA 34 mA 34 mA RPTP hex 3600 3600 3600 3600 3600 3600 decimal 15.4 ms 12.3 ms 8.96 ms 7.5 ms 5 ms 4.8 ms RTDI hex 0F 0B 09 07 05 05
Pulse Metering Generation
There is an additional tone generator suitable for generating tones above the audio frequency. This oscillator is provided for the generation of billing tones which are typically 12 kHz or 16 kHz. The generator follows the same algorithm as described in "Tone Generation" on page 32 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz. The equations are as follows:
2f coeff = cos ------------------------- 64000 Hz PLSCO = coeff ( 2
15
The initial phase of the pulse metering signal is set to 0 internally so there is no register to serve this purpose. The pulse metering generator timers and associated pulse metering timer registers are similar to that of the tone generators. These timers count 8 kHz sample periods like the other tones even though the sinusoid is generated at 64 kHz.
- 1)
Desired V RMS 1 1 - coeff 15 PLSX = -- ----------------------- ( 2 - 1 ) ---------------------------------------------Full Scale V RMS 4 1 + coeff
where full scale VRMS = 0.85 VRMS for a matched load.
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Table 24. Associated Pulse Metering Generator Registers
Parameter Pulse Metering Frequency Coefficient Pulse Metering Amplitude Coefficient Pulse Metering Attack/Decay Ramp Rate Pulse Metering Active Timer Pulse Metering Inactive Timer Pulse Metering Control Description / Range Sets oscillator frequency Sets oscillator amplitude 0 to PLSX (full amplitude) 0 to 8 sec 0 to 8 sec Status and control registers Register Bits PLSCO[15:0] PLSX[15:0] PLSD[15:0] PAT[15:0] PIT[15:0] PSTAT, PMAE, PMIE, PMOE Location Indirect Register 25 Indirect Register 24 Indirect Register 23 Direct Registers 44 & 45 Direct Register 46 & 47 Direct Register 35
Note: The ProSLIC uses registers that are both directly and indirectly mapped. A "direct" register is one that is mapped directly. An "indirect" register is one that is accessed using the indirect access registers (direct registers 28 through 31).
The pulse metering oscillator has a volume envelope (linear ramp) on the on/off transitions of the oscillator. The volume value is incremented by the value in the PLSD register (indirect Register 23) at an 8 kHz rate. The sinusoidal generator output is multiplied by this volume before being sent to the DAC. The volume will ramp from 0 to 7FFF in increments of PLSD so the value of PLSD will set the slope of the ramp. When the pulse metering signal is turned off, the volume will ramp to 0 by decrementing according to the value of PLSD.
DTMF Detection
The dual-tone multi-frequency (DTMF) tone signaling standard is also known as touch tone. It is an in-band signaling system used to replace the pulse-dial signaling standard. In DTMF, two tones are used to generate a DTMF digit. One tone is chosen from four possible row tones, and one tone is chosen from four possible column tones. The sum of these tones constitutes one of 16 possible DTMF digits. DTMF Detection Architecture DTMF detection is performed using a modified Goertzel algorithm to compute the dual frequency tone (DFT) for each of the eight DTMF frequencies as well as their second harmonics. At the end of the DFT computation, the squared magnitudes of the DFT results for the eight DTMF fundamental tones are computed. The row results are sorted to determine the strongest row frequency; the column frequencies are sorted as well. At the completion of this process, a number of checks are made to determine whether the strongest row and column tones constitute a DTMF digit. The detection process is performed twice within the 45 ms minimum tone time. A digit must be detected on two consecutive tests following a pause to be recognized as a new digit. If all tests pass, an interrupt is generated, and the DTMF digit value is loaded into the DTMF register. If tones are occurring at the maximum rate of 100 ms per digit, the interrupt must be serviced within 85 ms so that the current digit is not
39
Pulse Metering Oscillator
X
To DAC Volum e 8 Khz
+/-
PLSD
Clip to 7FFF or 0
Figure 21. Pulse Metering Volume Envelope
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overwritten by a new one. There is no buffering of the digit information.
Audio Path
Unlike traditional SLICs, the codec function is integrated into the ProSLIC. The 16-bit codec offers programmable gain/attenuation blocks and several loop-back modes. The signal path block diagram is shown in Figure 22. Transmit Path In the transmit path, the analog signal fed by the external AC coupling capacitors is amplified by the analog transmit amplifier, ATX, prior to the A/D converter. The gain of the ATX is user selectable to one of mute/-3.5/0/3.5 dB options. The main role of ATX is to coarsely adjust the signal swing to be as close as possible to the full-scale input of the A/D converter in order to maximize the signal-to-noise ratio of the transmit path. After passing through an anti-aliasing filter, the analog signal is processed by the A/D converter, producing an 8 kHz, 16-bit wide, linear PCM data stream. The standard requirements for transmit path attenuation for signals above 3.4 kHz are implemented as part of the combined decimation filter characteristic of the A/D converter. One more digital filter is available in the transmit path: THPF. THPF implements the high-pass attenuation requirements for signals below 65 Hz. The linear PCM data stream output from THPF is amplified by the transmit-path programmable gain amplifier, ADCG, which can be programmed from -6 dB to 6 dB. The DTMF decoder can receive the linear PCM data stream at this point to perform the digit extraction when enabled by the user. The final step in the transmit path signal processing is the user selectable A-law or -law compression which can reduce the data stream word width to 8 bits. Depending on the PCM_Mode register selection, every 8-bit compressed serial data word will occupy one time slot on the PCM highway, or every 16-bit uncompressed serial data word will occupy two time slots on the PCM highway.
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Transmit Path Off Chip On Chip From Billing Tone DAC HYBP H DTMF Decoder
ATX
+-
A/D
Decimation Filter
THPF
ADCG
Mute
+
/A-law Compressor
Serial Output
Digital TX
Analog Loopback
Digital Loopback
RXM Full Analog Loopback
H
HYBA
ALM1
DLM
Dual Tone Generator
ALM2
TIP RING
XAC
ARX -
+
From Billing Tone DAC
D/A
Interpolation Filter
RHPF
DACG
+
Mute
/A-law Expander
Serial Input
Digital RX
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Ibuf
Gm
RAC TXM
Figure 22. AC Signal Path Block Diagram
SI3210/Si3211/Si3212
Si3 21 0/Si3 211/Si321 2
Receive Path In the receive path, the optionally compressed 8-bit data is first expanded to 16-bit words. The PCMF register bit can bypass the expansion process, in which case two 8-bit words are assembled into one 16-bit word. DACG is the receive path programmable gain amplifier which can be programmed from -6 dB to 6 dB. An 8 kHz, 16bit signal is then provided to a D/A converter. The resulting analog signal is amplified by the analog receive amplifier, ARX, which is user selectable to one of mute/-3.5/0/3.5 dB options. It is then applied at the input of the transconductance amplifier (Gm) which drives the off-chip current buffer (IBUF). Audio Characteristics The dominant source of distortion and noise in both the transmit and receive paths is the quantization noise introduced by the -law or the A-law compression process. Figure 1 on page 7 specifies the minimum signal-to-noise-and-distortion ratio for either path for a sine wave input of 200 Hz to 3400 Hz. Both the -law and the A-law speech encoding allow the audio codec to transfer and process audio signals larger than 0 dBm0 without clipping. The maximum PCM code is generated for a -law encoded sine wave of 3.17 dBm0 or an A-law encoded sine wave of 3.14 dBm0. The ProSLIC overload clipping limits are driven by the PCM encoding process. Figure 2 on page 7 shows the acceptable limits for the analog-to-analog fundamental power transfer-function, which bounds the behavior of ProSLIC. The transmit path gain distortion versus frequency is shown in Figure 3 on page 8. The same figure also presents the minimum required attenuation for any outof-band analog signal that may be applied on the line. Note the presence of a high-pass filter transfer-function, which ensures at least 30 dB of attenuation for signals below 65 Hz. The low-pass filter transfer function which attenuates signals above 3.4 kHz has to exceed the requirements specified by the equations in Figure 3 on page 8 and it is implemented as part of the A-to-D converter. The receive path transfer function requirement, shown in Figure 4 on page 9, is very similar to the transmit path transfer function. The most notable difference is the absence of the high-pass filter portion. The only other differences are the maximum 2 dB attenuation at 200 Hz (as opposed to 3 dB for the transmit path) and the 28 dB of attenuation for any frequency above 4.6 kHz. The PCM data rate is 8 kHz and thus, no frequencies greater than 4 kHz can be digitally encoded in the data stream. From this point of view, at frequencies greater than 4 kHz, the plot in Figure 4
42
should be interpreted as the maximum allowable magnitude of any spurious signals that are generated when a PCM data stream representing a sine wave signal in the range of 300 Hz to 3.4 kHz at a level of 0 dBm0 is applied at the digital input. The group delay distortion in either path is limited to no more than the levels indicated in Figure 5 on page 10. The reference in Figure 5 is the smallest group delay for a sine wave in the range of 500 Hz to 2500 Hz at 0 dBm0. The block diagram for the voice-band signal processing paths are shown in Figure 22. Both the receive and the transmit paths employ the optimal combination of analog and digital signal processing to provide the maximum performance while, at the same time, offering sufficient flexibility to allow users to optimize for their particular application of the ProSLIC. All programmable signal-processing blocks are symbolically indicated in Figure 22 by a dashed arrow across them. The two-wire (TIP/RING) voice-band interface to the ProSLIC is implemented using a small number of external components. The receive path interface consists of a unity-gain current buffer, IBUF, while the transmit path interface is simply an AC coupling capacitor. Signal paths, although implemented differentially, are shown as single-ended for simplicity. Transhybrid Balance The ProSLIC provides programmable transhybrid balance with gain block H. (See Figure 22.) In the ideal case where the synthesized SLIC impedance matches exactly the subscriber loop impedance, the transhybrid balance should be set to subtract a -6 dB level from the transmit path signal. The transhybrid balance gain can be adjusted from -2.77 dB to +4.08 dB around the ideal setting of -6 dB by programming the HYBA[2:0] bits of the Hybrid Control register (direct Register 11). Note that adjusting any of the analog or digital gain blocks will not require any modification of the transhybrid balance gain block, as the transhybrid gain is subtracted from the transmit path signal prior to any gain adjustment stages. The transhybrid balance can also be disabled, if desired, using the appropriate register setting. Loopback Testing Four loopback test options are available in the ProSLIC:
!
The full analog loopback (ALM2) tests almost all the circuitry of both the transmit and receive paths. The compressed 8-bit word transmit data stream is fed back serially to input of the receive path expander. (See Figure 22.) The signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output of the
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!
!
!
receive path. An additional analog loopback (ALM1) takes the digital stream at the output of the A/D converter and feeds it back to the D/A converter. (See Figure 22.) The signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output of the receive path. This loopback option allows the testing of the analog signal processing circuitry of the SI3210 completely independent from any activity in the DSP. The full digital loopback tests almost all the circuitry of both the transmit and receive paths. The analog signal at the output of the receive path is fed back to the input of the transmit path by way of the hybrid filter path. (See Figure 22.) The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. The user can bypass the companding process and interface directly to the 16-bit data. An additional digital loopback (DLM) takes the digital stream at the input of the D/A converter in the receive path and feeds it back to the transmit A/D digital filter. The signal path starts with 8-bit PCM data input to the receive path and ends with 8-bit PCM data at the output of the transmit path. This loopback option allows the testing of the digital signal processing circuitry of the SI3210 completely independent from any analog signal processing activity.The user can bypass the companding process and interface directly to the 16-bit data.
The ProSLIC also provides a means to compensate for degraded subscriber loop conditions involving excessive line capacitance (leakage). The CLC[1:0] bits of direct Register 10 increase the AC signal magnitude to compensate for the additional loss at the high end of the audio frequency range. The default setting of CLC[2:0] assumes no line capacitance. Silicon revisions C and higher support the option to remove the internal reference resistor used to synthesize AC impedances for 600 + 2.16 F and 900 + 2.16 F settings so that an external resistor reference may be used. This option is enabled by setting ZSEXT = 1 (direct Register 108, bit 4).
Clock Generation
The ProSLIC will generate the necessary internal clock frequencies from the PCLK input. PCLK must be synchronous to the 8 kHz FSYNC clock and run at one of the following rates: 256 kHz, 512 kHz, 768 kHz, 1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or 8.192 MHz. The ratio of the PCLK rate to the FSYNC rate is determined via a counter clocked by PCLK. The three-bit ratio information is automatically transferred into an internal register, PLL_MULT, following a reset of the ProSLIC. The PLL_MULT is used to control the internal PLL which multiplies PCLK as needed to generate 16.384 MHz rate needed to run the internal filters and other circuitry. The PLL clock synthesizer settles very quickly following power up. However, the settling time depends on the PCLK frequency and it can be approximately predicted by the following equation:
64 TSETTLE = ---------------F PCLK
Two-Wire Impedance Matching
The ProSLIC provides on-chip programmable two-wire impedance settings to meet a wide variety of worldwide two-wire return loss requirements. The two-wire impedance is programmed by loading one of the eight available impedance values into the TISS[2:0] bits of the Two-Wire Impedance Synthesis Control register (direct Register 10). If direct Register 10 is not userdefined, the default setting of 600 will be loaded into the TISS register. Real and complex two-wire impedances are realized by internal feedback of a programmable amplifier (RAC) a switched capacitor network (XAC) and a transconductance amplifier (Gm). (See Figure 22.) RAC creates the real portion and XAC creates the imaginary portion of Gm's input. Gm then creates a current that models the desired impedance value to the subscriber loop. The differential AC current is fed to the subscriber loop via the ITIPP and IRINGP pins through an off-chip current buffer (IBUF), which is implemented using transistor Q1 and Q2 (see Figure 9 on page 18). Gm is referenced to an off-chip resistor (R15).
Interrupt Logic
The ProSLIC is capable of generating interrupts for the following events:
! ! ! ! ! ! ! ! ! ! ! !
Loop current/ring ground detected Ring trip detected Power alarm DTMF digit detected (SI3210 and Si3211 only) Active timer 1 expired Inactive timer 1 expired Active timer 2 expired Inactive timer 2 expired Ringing active timer expired Ringing inactive timer expired Pulse metering active timer expired Pulse metering inactive timer expired
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Preliminary Rev. 0.9
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Indirect register access complete The interface to the interrupt logic consists of six registers. Three interrupt status registers contain 1 bit for each of the above interrupt functions. These bits will be set when an interrupt is pending for the associated resource. Three interrupt enable registers also contain 1 bit for each interrupt function. In the case of the interrupt enable registers, the bits are active high. Refer to the appropriate functional description section for operational details of the interrupt functions.
!
There are a number of variations of usage on this fourwire interface:
!
!
When a resource reaches an interrupt condition, it will signal an interrupt to the interrupt control block. The interrupt control block will then set the associated bit in the interrupt status register if the enable bit for that interrupt is set. The INT pin is a NOR of the bits of the interrupt status registers. Therefore, if a bit in the interrupt status registers is asserted, IRQ will assert low. Upon receiving the interrupt, the interrupt handler should read interrupt status registers to determine which resource is requesting service. To clear a pending interrupt, write the desired bit in the appropriate interrupt status register to 1. Writing a 0 has no effect. This provides a mechanism for clearing individual bits when multiple interrupts occur simultaneously. While the interrupt status registers are non-zero, the INT pin will remain asserted.
!
Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read cycle, and must remain low for the duration of the 8 bit transfer (command/address or data). SDI/SDO wired operation. Independent of the clocking options described, SDI and SDO can be treated as two separate lines or wired together if the master is capable of tristating its output during the data byte transfer of a read operation. Daisy chain mode. This mode allows communication with banks of up to eight ProSLIC devices using one chip select signal. When the SPIDC bit in the SPI Mode Select register is set, data transfer mode changes to a 3-byte operation: a chip select byte, an address/control byte, and a data byte. Using the circuit shown in Figure 25, a single device may select from the bank of devices by setting the appropriate chip select bit. Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered.
Serial Peripheral Interface
The control interface to the ProSLIC is a 4-wire interface modeled after commonly available micro-controller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). Data is transferred a byte at a time with each register access consisting of a pair of byte transfers. Figures 23 and 24 illustrate read and write operation in the SPI bus. The first byte of the pair is the command/address byte. The MSB of this byte indicates register read when 1 and a register write when 0. The remaining seven bits of the command/address byte indicate the address of the register to be accessed. The second byte of the pair is the data byte. During a read operation, the SDO becomes active and the 8-bit contents of the register are driven out MSB first. The SDO will be high impedence on either the falling edge of SCLK following the LSB, or the rising of CS whichever comes first. SDI is a "don't care" during the data portion of read operations. During write operations, data is driven into the ProSLIC via the SDI pin MSB first. The SDO pin will remain high impedance during write operations. Data always transitions with the falling edge of the clock and is latched on the rising edge. The clock should return to a logic high when no transfer is in progress.
44 Preliminary Rev. 0.9
SI3210/Si3211/Si3212
SCLK
CS
SDI
0
a6
a5
a4
a3
a2
a1
a0
d7
d6
d5
d4
d3
d2
d1
d0
SDO
H igh Im pedance
Figure 23. Serial Write 8-Bit Mode
SCLK
CS
SDI
1
a6
a5
a4
a3
a2
a1
a0
D o n 't C are
SDO
H igh Im pedance
d7
d6
d5
d4
d3
d2
d1
d0
Figure 24. Serial Read 8-Bit Mode
Preliminary Rev. 0.9
45
Si3 21 0/Si3 211/Si321 2
SDO CPU CS SDI
CS SDO
SDI
SDI0
SDIT HRU
CS SDO
SDI
SDI1
SDIT HRU
CS SDO
SDI
SDI2
SDIT HRU
CS SDO
SDI
SDI3
SDIT HRU
Chip Select Byte SCLK
Address Byte
Data Byte
SDI0
C7 C 6 C5 C4 C3 C 2 C1 C0
R /W
A6 A5 A4 A3 A2 A1 A0
D7 D 6 D5 D4 D3 D 2 D1 D0
SDI1
- C7 C 6 C 5 C4 C3 C 2 C1
R /W
A6 A5 A4 A3 A2 A1 A0
D7 D 6 D5 D4 D3 D 2 D1 D0
SDI2
-
-
C7 C6 C 5 C4 C3 C 2
R /W
A6 A5 A4 A3 A2 A1 A0
D7 D 6 D5 D4 D3 D 2 D1 D0
SDI3
-
-
-
C7 C6 C 5 C 4 C3
R /W
A6 A5 A4 A3 A2 A1 A0
D7 D 6 D5 D4 D3 D 2 D1 D0
Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select.
Figure 25. SPI Daisy Chain Mode
46
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
PCM Interface
The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM Mode Select (direct Register 1), PCM Transmit Start Count (direct registers 2 and 3), and PCM Receive Start Count (direct registers 4 and 5) registers. The interface can be configured to support from 4 to 128 8-bit timeslots in each frame. This corresponds to PCLK frequencies of 256 kHz to 8.192 MHz in power of 2 increments. (768 kHz and 1.536 MHz are also available.) Timeslots for data transmission and reception are independently configured using the TXS and RXS registers. By setting the correct starting point of the data, the ProSLIC can be configured to support long FSYNC and short FSYNC variants as well as IDL2 8-bit, 10-bit, B1 and B2 channel time slots. DTX data is high impedance except for the duration of the 8-bit PCM transmit. DTX will return to high impedance either on the negative edge of PCLK
PCLK
during the LSB, or on the positive edge of PCLK following the LSB. This is based on the setting of the TRI bit of the PCM Mode Select register. Tristating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots without the risk of driver contention. In addition to 8-bit data modes, there is a 16-bit mode provided for testing. This mode can be activated via the PCMT bit of the PCM Mode Select register. GCI timing is also supported in which the duration of a data bit is two PCLK cycles. This mode is also activated via the PCM Mode Select register. Setting the TXS or RXS register greater than the number of PCLK cycles in a sample period will stop data transmission because TXS or RXS will never equal the PCLK count. Figures 26-29 illustrate the usage of the PCM highway interface to adapt to common PCM standards.
FS Y N C
P C L K _C N T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
M SB LSB
DTX
H I-Z M SB LSB H I-Z
Figure 26. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
P CL K
FSYNC
P CL K _C N T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
M SB LSB
DTX
H I-Z M SB LSB H I-Z
Figure 27. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
Preliminary Rev. 0.9 47
Si3 21 0/Si3 211/Si321 2
PCLK
FS Y N C
P C L K _C N T
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DRX
M SB LSB
DTX
H I-Z M SB LSB
H I-Z
Figure 28. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
PCLK
FSYNC
PCLK_CNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D RX
M SB LSB
D TX
H I-Z M SB LSB H I-Z
Figure 29. GCI Example, Timeslot 1 (TXS/RXS = 0)
Companding
The ProSLIC supports both -255 Law and A-Law companding formats in addition to linear data. These 8bit companding schemes follow a segmented curve formatted as sign bit, three chord bits, and four step bits. -255 Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is selected via the PCMF register. Tables 25 and 26 define the -Law and A-Law encoding formats.
48
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Table 25. -Law Encode-Decode Characteristics1,2
Segment Number
8
#Intervals X Interval Size
16 X 256
Value at Segment Endpoints
8159 . . . 4319 4063 . . . 2143 2015 . . . 1055 991 . . . 511 479 . . . 239 223 . . . 103 95 . . . 35 31 . . . 3 1 0
Digital Code
10000000b
Decode Level
8031
10001111b
4191
7
16 X 128
10011111b
2079
6
16 X 64
10101111b
1023
5
16 X 32
10111111b
495
4
16 X 16
11001111b
231
3
16 X 8
11011111b
99
2
16 X 4
11101111b
33
1
15 X 2
__________________ 1X1
11111110b 11111111b
2 0
Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all magnitude bits.
Preliminary Rev. 0.9
49
Si3 21 0/Si3 211/Si321 2
Table 26. A-Law Encode-Decode Characteristics1,2
Segment Number 7 #intervals X interval size 16 X 128 Value at segment endpoints 4096 3968 . . 2176 2048 . . . 1088 1024 . . . 544 512 . . . 272 256 . . . 136 128 . . . 68 64 . . . 2 0 Digital Code Decode Level
10101010b
4032
10100101b
2112
6
16 X 64
10110101b
1056
5
16 X 32
10000101b
528
4
16 X 16
10010101b
264
3
16 X 8
11100101b
132
2
16 X 4
11110101b
66
1
32 X 2
11010101b
1
Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of all even numbered bits.
50
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Control Registers
Note: Any register not listed here is reserved and must not be written.
Table 27. Register Summary
Register Name 0 1 2 3 4 5 6 SPI Mode Select PCM Mode Select PCM Transmit Start Count--Low Byte PCM Transmit Start Count--High Byte PCM Receive Start Count--Low Byte PCM Receive Start Count--High Byte Digital Input/Output Control Audio 8 9 10 11 14 15 18 19 20 21 22 23 24 Audio Path Loopback Control Audio Gain Control Two-Wire Impedance Synthesis Control Hybrid Control Power Down Control 1 Power Down Control 2 Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 Interrupt Enable 1 Interrupt Enable 2 Interrupt Enable 3 Decode Status VAL2 PMIE Q6AE PMAE Q5AE RGIE Q4AE RGAE Q3AE O2IE Q2AE PMIP Q6AP PMAP Q5AP RXHP TXHP TXM RXM CLC[1:0] HYBP[2:0] Powerdown PMON ADCM Interrupts RGIP Q4AP RGAP Q3AP O2IP Q2AP O2AP Q1AP CMCP O2AE Q1AE CMCE O1IP LCIP INDP O1IE LCIE INDE O1AP RTIP DTMFP2 O1AE RTIE DTMFE2 DCOF1 ADCON MOF DACM PLLOF DACON BIASOF SLICOF GMM GMON TISE ALM2 ATX[1:0] DLM ALM1 DOUT DIO2 DIO1 RXS[7:0] RXS[9:8] PD2 PD1 Bit 7 SPIDC Bit 6 SPIM Bit 5 Setup PNI[1:0] PCME PCMF[1:0] TXS[7:0] TXS[9:8] RNI[3:0] PCMT GCI TRI Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ARX[1:0] TISS[2:0] HYBA[2:0]
DIG[3:0]2
Notes: 1. SI3210 only. 2. SI3210 and Si3211 only.
Preliminary Rev. 0.9
51
Si3 21 0/Si3 211/Si321 2
Table 27. Register Summary (Continued)
Register Name 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Indirect Data Access-- Low Byte Indirect Data Access-- High Byte Indirect Address Indirect Address Status Oscillators Oscillator 1 Control Oscillator 2 Control Ringing Oscillator Control Pulse Metering Oscillator Control Oscillator 1 Active Timer--Low Byte Oscillator 1 Active Timer--High Byte Oscillator 1 Inactive Timer--Low Byte Oscillator 1 Inactive Timer--High Byte Oscillator 2 Active Timer--Low Byte Oscillator 2 Active Timer--High Byte Oscillator 2 Inactive Timer--Low Byte Oscillator 2 Inactive Timer--High Byte Pulse Metering Oscillator Active Timer-- Low Byte Pulse Metering Oscillator Active Timer-- High Byte OSS1 OSS2 RSS PSTAT REL OZ1 OZ2 RDAC O1TAE O2TAE RTAE PMAE O1TIE O2TIE RTIE PMIE O1E O2E ROE PMOE O1SO[1:0] O2SO[1:0] RVO TSWS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Indirect Register Access IDA[7:0] IDA[15:8] IAA[7:0] IAS
OAT1[7:0] OAT1[15:8] OIT1[7:0] OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] PAT[7:0]
45
PAT[15:8]
Notes: 1. SI3210 only. 2. SI3210 and Si3211 only.
52
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Table 27. Register Summary (Continued)
Register Name 46 Pulse Metering Oscillator Inactive Timer--Low Byte Pulse Metering Oscillator Inactive Timer--High Byte Ringing Oscillator Active Timer--Low Byte Ringing Oscillator Active Timer--High Byte Ringing Oscillator Inactive Timer--Low Byte Ringing Oscillator Inactive Timer--High Byte FSK Data SLIC 63 Loop Closure Debounce Interval for Automatic Ringing Linefeed Control External Bipolar Transistor Control Battery Feed Control Automatic/Manual Control Loop Closure/Ring Trip Detect Status Loop Closure Debounce Interval Ring Trip Detect Debounce Interval Loop Current Limit On-Hook Line Voltage Common Mode Voltage High Battery Voltage Low Battery Voltage Power Monitor Pointer VSGN VOC[5:0] VCM[5:0] VBATH[5:0] VBATL[5:0] PWRMP[2:0] MNCM MNDIF SQH LFS[2:0] CBY ETBE VOV SPDS ETBO[1:0] FVBAT1 EXTBAT1 ABAT AORD DBIRAW LCDI[6:0] RTDI[6:0] ILIM[2:0] LCD[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIT[7:0]
47
PIT[15:8]
48 49 50 51 52
RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] FSKDAT
64 65 66 67 68 69 70 71 72 73 74 75 76
LF[2:0] ETBA[1:0] BATSL AOLD RTP TRACK1 AOPN LCR
Notes: 1. SI3210 only. 2. SI3210 and Si3211 only.
Preliminary Rev. 0.9
53
Si3 21 0/Si3 211/Si321 2
Table 27. Register Summary (Continued)
Register Name 77 78 79 80 81 82 83 84 85 86 87 88 89 92 93 94 95 96 97 98 99 100 Line Power Output Monitor Loop Voltage Sense Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense 1 Battery Voltage Sense 2 Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense Transistor 4 Current Sense Transistor 5 Current Sense Transistor 6 Current Sense DC-to-DC Converter PWM Period DC-to-DC Converter Switching Delay PWM Pulse Width Reserved Calibration Control/ Status Register 1 Calibration Control/ Status Register 2 RING Gain Mismatch Calibration Result TIP Gain Mismatch Calibration Result Differential Loop Current Gain Calibration Result CAL CALSP CALR
CALM1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWROM[7:0] LVSP LCSP VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] IQ1[7:0] IQ2[7:0] IQ3[7:0] IQ4[7:0] IQ5[7:0] IQ6[7:0] DCN[7:0]1 DCCAL1 DCPOL1 DCPW[7:0]1 CALT
CALM2
LVS[5:0] LCS[5:0]
DCTOF[4:0]1
CALD
CALDAC
CALC
CALADC
CALIL
CALCM
CALGMR[R4:0] CALGMT[4:0] CALGD[4:0]
Notes: 1. SI3210 only. 2. SI3210 and Si3211 only.
54
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Table 27. Register Summary (Continued)
Register Name 101 Common Mode Loop Current Gain Calibration Result Current Limit Calibration Result Monitor ADC Offset Calibration Result Analog DAC/ADC Offset DAC Offset Calibration Result Common Mode Balance Calibration Result DC Peak Voltage Calibration Result Enhancement Enable ILIMEN FSKEN DCEN1 ZSEXT SWDB CALMG1[3:0] DACP DACOF[7:0] CMBAL[5:0] CMDCPK[3:0] LCVE DCFIL1 HYSTEN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CALGC[4:0] Bit 1 Bit 0
102 103 104 105 106 107 108
CALGIL[3:0] CALMG2[3:0] DACN ADCP ADCN
Notes: 1. SI3210 only. 2. SI3210 and Si3211 only.
Preliminary Rev. 0.9
55
Si3 21 0/Si3 211/Si321 2
Register 0. SPI Mode Select Bit Name Type D7 SPIDC R/W D6 SPIM R/W D5 PNI[1:0] R D4 D3 D2 RNI[3:0] R D1 D0
Reset settings = 00xx_xxxx Bit 7 Name SPIDC SPI Daisy Chain Mode Enable. 0 = Disable SPI daisy chain mode. 1 = Enable SPI daisy chain mode. SPI Mode. 0 = Causes SDO to tri-state on rising edge of SCLK of LSB. 1 = Normal operation; SDO tri-states on rising edge of CS. Part Number Identification. 00 = SI3210 01 = Si3211 10 = Si3212 11 = Reserved Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc. Function
6
SPIM
5:4
PNI[1:0]
3:0
RNI[3:0]
56
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 1. PCM Mode Select Bit Name Type Reset settings = 0000_1000 Bit 7:6 5 Name Reserved PCME Read returns zero. PCM Enable. 0 = Disable PCM transfers. 1 = Enable PCM transfers. PCM Format. 00 = A-Law 01 = -Law 10 = Reserved 11 = Linear PCM Transfer Size. 0 = 8-bit transfer. 1 = 16-bit transfer. GCI Clock Format. 0 = 1 PCLK per data bit. 1 = 2 PCLKs per data bit. Tri-state Bit 0. 0 = Tri-state bit 0 on positive edge of PCLK. 1 = Tri-state bit 0 on negative edge of PCLK. Function D7 D6 D5 PCME R/W D4 D3 D2 PCMT R/W D1 GCI R/W D0 TRI R/W
PCMF[1:0] R/W
4:3
PCMF[1:0]
2
PCMT
1
GCI
0
TRI
Register 2. PCM Transmit Start Count--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name TXS[7:0] Function PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 26 on page 47. D7 D6 D5 D4 TXS[7:0] R/W D3 D2 D1 D0
Preliminary Rev. 0.9
57
Si3 21 0/Si3 211/Si321 2
Register 3. PCM Transmit Start Count--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:2 1:0 Name Reserved TXS[9:8] Read returns zero. PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 26 on page 47. Function D7 D6 D5 D4 D3 D2 D1 D0 TXS[9:8] R/W
Register 4. PCM Receive Start Count--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RXS[7:0] Function PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 26 on page 47. D7 D6 D5 D4 D3 D2 D1 D0
RXS[7:0] R/W
Register 5. PCM Receive Start Count--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:2 1:0 Name Reserved RXS[9:8] Read returns zero. PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 26 on page 47. Function D7 D6 D5 D4 D3 D2 D1 D0
RXS[9:8] R/W
58
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 6. Digital Input/Output Control Bit Name Type Reset settings = 0000_0000 Bit 7:5 4 Name Reserved DOUT Read returns zero. DOUT Pin Output Data. Digital I/O pins are available when EXTBAT = 1. 0 = DOUT pin driven low. 1 = DOUT pin driven high. DIO2 Pin Input/Output Direction. Digital I/O pins are available when EXTBAT = 1. 0 = DIO2 pin is an input. 1 = DIO2 pin is an output and driven to value of the PD2 bit. DIO1 Pin Input/Output Direction. Digital I/O pins are available when EXTBAT = 1. 0 = DIO1 pin is an input. 1 = DIO1 pin is an output and driven to value of the PD1 bit. DIO2 Pin Data. Digital I/O pins are available when EXTBAT = 1. When DIO2 = 1: 0 = DIO2 pin driven low. 1 = DIO2 pin driven high. When DIO2 = 0, PD2 value equals the logic input of DIO2 pin. DIO1 Pin Data. Digital I/O pins are available when EXTBAT = 1. When DIO1 = 1: 0 = DIO1 pin driven low. 1 = DIO1 pin driven high. When DIO1 = 0, PD1 value equals the logic input of DIO1 pin. Function D7 D6 D5 D4 DOUT R/W D3 DIO2 R/W D2 DIO1 R/W D1 PD2 R/W D0 PD1 R/W
3
DIO2
2
DIO1
1
PD2
0
PD1
Preliminary Rev. 0.9
59
Si3 21 0/Si3 211/Si321 2
Register 8. Audio Path Loopback Control Bit Name Type Reset settings = 0000_0010 Bit 7:3 2 Name Reserved ALM2 Read returns zero. Analog Loopback Mode 2. (See Figure 22 on page 41.) 0 = Full analog loopback mode disabled. 1 = Full analog loopback mode enabled. Digital Loopback Mode. (See Figure 22 on page 41.) 0 = Digital loopback disabled. 1 = Digital loopback enabled. Analog Loopback Mode 1. (See Figure 22 on page 41.) 0 = Analog loopback disabled. 1 = Analog loopback enabled. Function D7 D6 D5 D4 D3 D2 ALM2 R/W D1 DLM R/W D0 ALM1 R/W
1
DLM
0
ALM1
60
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 9. Audio Gain Control Bit Name Type D7 RXHP R/W D6 TXHP R/W D5 TXM R/W D4 RXM R/W D3 ATX[1:0] R/W D2 D1 D0
ARX[1:0] R/W
Reset settings = 0000_0000 Bit 7 Name RXHP Function Receive Path High Pass Filter Disable. 0 = HPF enabled in receive path, RHDF. 1 = HPF bypassed in receive path, RHDF. Transmit Path High Pass Filter Disable. 0 = HPF enabled in transmit path, THPF. 1 = HPF bypassed in transmit path, THPF. Transmit Path Mute. Refer to position of digital mute in Figure 22 on page 41. 0 = Transmit signal passed. 1 = Transmit signal muted. Receive Path Mute. Refer to position of digital mute in Figure 22 on page 41. 0 = Receive signal passed. 1 = Receive signal muted. Analog Transmit Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = ATX gain = 0 dB; analog transmit path muted. Analog Receive Path Gain. 00 = 0 dB 01 = -3.5 dB 10 = 3.5 dB 11 = Analog receive path muted.
6
TXHP
5
TXM
4
RXM
3:2
ATX[1:0]
1:0
ARX[1:0]
Preliminary Rev. 0.9
61
Si3 21 0/Si3 211/Si321 2
Register 10. Two-Wire Impedance Synthesis Control Bit Name Type Reset settings = 0000_1000 Bit 7:6 5:4 Name Reserved CLC[1:0] Read returns zero. Line Capacitance Compensation. 00 = Off 01 = 4.7 nF 10 = 10 nF 11 = Reserved Two-Wire Impedance Synthesis Enable. 0 = Two-wire impedance synthesis disabled. 1 = Two-wire impedance synthesis enabled. Two-Wire Impedance Synthesis Selection. 000 = 600 001 = 900 010 = 600 + 2.16 F 011 = 900 + 2.16 F 100 = CTR21 (270 + 750 || 150 nF) 101 = Australia/New Zealand #1 (220 + 820 || 120 nF) 110 = Slovakia/Slovenia/South Africa (220 + 820 || 115 nF) 111 = New Zealand #2 (370 + 620 || 310 nF) Function D7 D6 D5 D4 D3 TISE R/W D2 D1 TISS[2:0] R/W D0
CLC[1:0] R/W
3
TISE
2:0
TISS[2:0]
62
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 11. Hybrid Control Bit Name Type Reset settings = 0011_0011 Bit 7 6:4 Name Reserved HYBP[2:0] Read returns zero. Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off Read returns zero. Audio Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = -1.02 dB 101 = -1.94 dB 110 = -2.77 dB 111 = Off Function D7 D6 D5 HYBP[2:0] R/W D4 D3 D2 D1 HYBA[2:0] R/W D0
3 2:0
Reserved HYBA[2:0]
Preliminary Rev. 0.9
63
Si3 21 0/Si3 211/Si321 2
Register 14. Power Down Control 1 SI3210 Bit Name Type Reset settings = 0001_0000 Si3211/Si3212 Bit Name Type Reset settings = 0001_0000 Bit 7:6 5 Name Reserved PMON Read returns zero. Pulse Metering DAC Power-On Control. 0 = Automatic power control. 1 = Override automatic control and force pulse metering DAC circuitry on. DC-to-DC Converter Power-Off Control (SI3210 only). 0 = Automatic power control. 1 = Override automatic control and force DC-to-DC circuitry off. Si3211/Si3212 = Read returns 1; it cannot be written. Monitor ADC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force monitor ADC circuitry off. PLL Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force PLL circuitry off. DC Bias Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force DC bias circuitry off. SLIC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force SLIC circuitry off. Function D7 D6 D5 PMON R/W D4 D3 MOF R/W D2 PLLOF R/W D1 BIASOF R/W D0 SLICOF R/W D7 D6 D5 PMON R/W D4 DCOF R/W D3 MOF R/W D2 PLLOF R/W D1 BIASOF R/W D0 SLICOF R/W
4
DCOF
3
MOF
2
PLLOF
1
BIASOF
0
SLICOF
64
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 15. Power Down Control 2 Bit Name Type Reset settings = 0000_0000 Bit 7:6 5 Name Reserved ADCM Read returns zero. Analog to Digital Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; ADCON controls on/off state. Analog to Digital Converter On/Off Power Control. When ADCM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. ADCON has no effect when ADCM = 0. Digital to Analog Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; DACON controls on/off state. Digital to Analog Converter On/Off Power Control. When DACM = 1: 0 = Digital to analog converter powered off. 1 = Digital to analog converter powered on. DACON has no effect when DACM = 0. Transconductance Amplifier Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; GMON controls on/off state. Transconductance Amplifier On/Off Power Control. When GMM = 1: 0 = Analog to digital converter powered off. 1 = Analog to digital converter powered on. GMON has no effect when GMM = 0. Function D7 D6 D5 ADCM R/W D4 ADCON R/W D3 DACM R/W D2 DACON R/W D1 GMM R/W D0 GMON R/W
4
ADCON
3
DACM
2
DACON
1
GMM
0
GMON
Preliminary Rev. 0.9
65
Si3 21 0/Si3 211/Si321 2
Register 18. Interrupt Status 1 Bit Name Type D7 PMIP R/W D6 PMAP R/W D5 RGIP R/W D4 RGAP R/W D3 O2IP R/W D2 O2AP R/W D1 O1IP R/W D0 O1AP R/W
Reset settings = 0000_0000 Bit 7 Name PMIP Function Pulse Metering Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Pulse Metering Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ringing Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 2 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
6
PMAP
5
RGIP
4
RGAP
3
O2IP
2
O2AP
1
O1IP
0
O1AP
66
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 19. Interrupt Status 2 Bit Name Type D7 Q6AP R/W D6 Q5AP R/W D5 Q4AP R/W D4 Q3AP R/W D3 Q2AP R/W D2 Q1AP R/W D1 LCIP R/W D0 RTIP R/W
Reset settings = 0000_0000 Bit 7 Name Q6AP Function Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q4 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q3 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q2 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Power Alarm Q1 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Loop Closure Transition Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Ring Trip Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
6
Q5AP
5
Q4AP
4
Q3AP
3
Q2AP
2
Q1AP
1
LCIP
0
RTIP
Preliminary Rev. 0.9
67
Si3 21 0/Si3 211/Si321 2
Register 20. Interrupt Status 3 SI3210/Si3211 Bit Name Type Reset settings = 0000_0000 Si3212 Bit Name Type Reset settings = 0000_0000 Bit 7:3 2 Name Reserved CMCP Read returns zero. Common Mode Calibration Error Interrupt. This bit is set when off-hook/on-hook status changes during the common mode balance calibration. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. DTMF Tone Detected Interrupt (SI3210 and Si3211 only). Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Si3212 = Reserved; read returns 0. Function D7 D6 D5 D4 D3 D2 CMCP R/W D1 INDP R/W D0 D7 D6 D5 D4 D3 D2 CMCP R/W D1 INDP R/W D0 DTMFP R/W
1
INDP
0
DTMFP
68
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 21. Interrupt Enable 1 Bit Name Type D7 PMIE R/W D6 PMAE R/W D5 RGIE R/W D4 RGAE R/W D3 O2IE R/W D2 O2AE R/W D1 O1IE R/W D0 O1AE R/W
Reset settings = 0000_0000 Bit 7 Name PMIE Function Pulse Metering Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Pulse Metering Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 2 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Oscillator 1 Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
6
PMAE
5
RGIE
4
RGAE
3
O2IE
2
O2AE
1
O1IE
0
O1AE
Preliminary Rev. 0.9
69
Si3 21 0/Si3 211/Si321 2
Register 22. Interrupt Enable 2 Bit Name Type D7 Q6AE R/W D6 Q5AE R/W D5 Q4AE R/W D4 Q3AE R/W D3 Q2AE R/W D2 Q1AE R/W D1 LCIE R/W D0 RTIE R/W
Reset settings = 0000_0000 Bit 7 Name Q6AE Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q3 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q2 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Power Alarm Q1 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Loop Closure Transition Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Ring Trip Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Function
6
Q5AE
5
Q4AE
4
Q3AE
3
Q2AE
2
Q1AE
1
LCIE
0
RTIE
70
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 23. Interrupt Enable 3 SI3210/Si3211 Bit Name Type Reset settings = 0000_0000 Si3212 Bit Name Type Reset settings = 0000_0000 Bit 7:3 2 Name Reserved CMCE Read returns zero. Common Mode Calibration Error Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Indirect Register Access Serviced Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. DTMF Tone Detected Interrupt Enable (SI3210 and Si3211 only). 0 = Interrupt masked. 1 = Interrupt enabled. Si3212 = Reserved. Function D7 D6 D5 D4 D3 D2 CMCE R/W D1 INDE R/W D0 D7 D6 D5 D4 D3 D2 CMCE R/W D1 INDE R/W D0 DTMFE R/W
1
INDE
0
DTMFE
Preliminary Rev. 0.9
71
Si3 21 0/Si3 211/Si321 2
Register 24. DTMF Decode Status SI3210/Si3211 Bit Name Type Reset settings = 0000_0000 Si3212 Bit Name Type Reset settings = 0000_0000 Bit 7:5 4 Name Reserved VAL Read returns zero. DTMF Valid Digit Decoded. 0 = Not currently detecting digit. 1 = Currently detecting digit. Si3212 = Reserved; read returns 0. DTMF Digit (SI3210 and Si3211 only). 0001 = "1" 0010 = "2" 0011 = "3" 0100 = "4" 0101 = "5" 0110 = "6" 0111 = "7" 1000 = "8" 1001 = "9" 1010 = "0" 1011 = "*" 1100 = "#" 1101 = "A" 1110 = "B" 1111 = "C" 0000 = "D" Si3212 = Reserved; read returns 0. Function D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 VAL R D3 D2 DIG[3:0] R D1 D0
3:0
DIG[3:0]
72
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 28. Indirect Data Access--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name IDA[7:0] Function Indirect Data Access--Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 IDA[7:0] R/W D3 D2 D1 D0
Register 29. Indirect Data Access--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name IDA[15:8] Function Indirect Data Access--High Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 D3 D2 D1 D0
IDA[15:8] R/W
Preliminary Rev. 0.9
73
Si3 21 0/Si3 211/Si321 2
Register 30. Indirect Address Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IAA[7:0] Function Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate--a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation). D7 D6 D5 D4 IAA[7:0] R/W D3 D2 D1 D0
Register 31. Indirect Address Status Bit Name Type Reset settings = 0000_0000 Bit 7:1 0 Name Reserved IAS Read returns zero. Indirect Access Status. 0 = No indirect memory access pending. 1 = Indirect memory access pending. Function D7 D6 D5 D4 D3 D2 D1 D0 IAS R
74
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 32. Oscillator 1 Control Bit Name Type D7 OSS1 R D6 REL R/W D5 OZ1 R/W D4 O1TAE R/W D3 O1TIE R/W D2 O1E R/W D1 D0
O1SO[1:0] R/W
Reset settings = 0000_0000 Bit 7 Name OSS1 Oscillator 1 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling. 0 = Oscillator 1 will stop signaling after inactive timer expires. 1 = Oscillator 1 will continue to read register parameters and output signals. Oscillator 1 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing after active timer expires. Oscillator 1 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 1 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 1 Signal Output Routing. 00 = Unassigned path (output not connected). 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Function
6
REL
5
OZ1
4
O1TAE
3
O1TIE
2
O1E
1:0
O1SO[1:0]
Preliminary Rev. 0.9
75
Si3 21 0/Si3 211/Si321 2
Register 33. Oscillator 2 Control Bit Name Type D7 OSS2 R D6 D5 OZ2 R/W D4 O2TAE R/W D3 O2TIE R/W D2 O2E R/W D1 D0
O2SO[1:0] R/W
Reset settings = 0000_0000 Bit 7 Name OSS2 Oscillator 2 Signal Status. 0 = Output signal inactive. 1 = Output signal active. Read returns zero. Oscillator 2 Zero Cross Enable. 0 = Signal terminates after active timer expires. 1 = Signal terminates at zero crossing. Oscillator 2 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Oscillator 2 Enable. 0 = Disable oscillator. 1 = Enable oscillator. Oscillator 2 Signal Output Routing. 00 = Unassigned path (output not connected) 01 = Assign to transmit path. 10 = Assign to receive path. 11 = Assign to both paths. Function
6 5
Reserved OZ2
4
O2TAE
3
O2TIE
2
O2E
1:0
O2SO[1:0]
76
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 34. Ringing Oscillator Control Bit Name Type D7 RSS R D6 D5 RDAC R D4 RTAE R/W D3 RTIE R/W D2 ROE R D1 RVO R/W D0 TSWS R/W
Reset settings = 0000_0000 Bit 7 Name RSS Function Ringing Signal Status. 0 = Ringing oscillator output signal inactive. 1 = Ringing oscillator output signal active. Read returns zero. Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure continuity with DC linefeed voltages. RDAC indicates that ringing signal is actually present at TIP and RING. 0 = Ringing signal not present at TIP and RING. 1 = Ringing signal present at TIP and RING. Ringing Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Ringing Oscillator Enable. 0 = Ringing oscillator disabled. 1 = Ringing oscillator enabled. Ringing Voltage Offset. 0 = No DC offset added to ringing signal. 1 = DC offset added to ringing signal. Trapezoid/Sinusoid Waveshape Select. 0 = Sinusoid 1 = Trapezoid
6 5
Reserved RDAC
4
RTAE
3
RTIE
2
ROE
1
RVO
0
TSWS
Preliminary Rev. 0.9
77
Si3 21 0/Si3 211/Si321 2
Register 35. Pulse Metering Oscillator Control Bit Name Type D7 PSTAT R D6 D5 D4 PMAE R/W D3 PMIE R/W D2 PMOE R/W D1 D0
Reset settings = 0000_0000 Bit 7 Name PSTAT Pulse Metering Signal Status. 0 = Output signal inactive. 1 = Output signal active. Read returns zero. Pulse Metering Active Timer Enable. 0 = Disable timer. 1 = Enable timer. Pulse Metering Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. Pulse Metering Oscillator Enable. 0 = Disable oscillator. 1 = Enable oscillator. Read returns zero. Function
6:5 4
Reserved PMAE
3
PMIE
2
PMOE
1:0
Reserved
78
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 36. Oscillator 1 Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OAT1[7:0] R/W
Register 37. Oscillator 1 Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT1[15:8] Oscillator 1 Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OAT1[15:8] R/W
Register 38. Oscillator 1 Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT1[7:0] Oscillator 1 Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OIT1[7:0] R/W
Preliminary Rev. 0.9
79
Si3 21 0/Si3 211/Si321 2
Register 39. Oscillator 1 Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT1[15:8] Oscillator 1 Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OIT1[15:8] R/W
Register 40. Oscillator 2 Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OAT2[7:0] R/W
Register 41. Oscillator 2 Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OAT2[15:8] Oscillator 2 Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OAT2[15:8] R/W
80
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 42. Oscillator 2 Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 D3 D2 D1 D0
OIT2[7:0] R/W
Register 43. Oscillator 2 Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name OIT2[15:8] Oscillator 2 Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
OIT2[15:8] R/W
Register 44. Pulse Metering Oscillator Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PAT[7:0] Pulse Metering Active Timer. LSB = 125 s Function D7 D6 D5 D4 PAT[7:0] R/W D3 D2 D1 D0
Preliminary Rev. 0.9
81
Si3 21 0/Si3 211/Si321 2
Register 45. Pulse Metering Oscillator Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PAT[15:8] Pulse Metering Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
PAT[15:8] R/W
Register 46. Pulse Metering Oscillator Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PIT[7:0] Pulse Metering Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 PIT[7:0] R/W D3 D2 D1 D0
Register 47. Pulse Metering Oscillator Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PIT[15:8] Pulse Metering Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
PIT[15:8] R/W
82
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 48. Ringing Oscillator Active Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RAT[7:0] Ringing Active Timer. LSB = 125 s Function D7 D6 D5 D4 RAT[7:0] R/W D3 D2 D1 D0
Register 49. Ringing Oscillator Active Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RAT[15:8] Ringing Active Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
RAT[15:8] R/W
Register 50. Ringing Oscillator Inactive Timer--Low Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RIT[7:0] Ringing Inactive Timer. LSB = 125 s Function D7 D6 D5 D4 RIT[7:0] R/W D3 D2 D1 D0
Preliminary Rev. 0.9
83
Si3 21 0/Si3 211/Si321 2
Register 51. Ringing Oscillator Inactive Timer--High Byte Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name RIT[15:8] Ringing Inactive Timer. Function D7 D6 D5 D4 D3 D2 D1 D0
RIT[15:8] R/W
Register 52. FSK Data Bit Name Type Reset settings = 0000_0000 Bit 7:1 0 Name Reserved FSKDAT Read returns zero. FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data. Function D7 D6 D5 D4 D3 D2 D1 D0 FSKDAT R/W
Register 63. Loop Closure Debounce Interval Bit Name Type Reset settings = 0011_0010 (revision C) Bit 7:0 0101_0100 (revision D) Name LCD[7:0] Function D7 D6 D5 D4 D3 D2 D1 D0
LCD[7:0]
Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps.
84
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 64. Linefeed Control Bit Name Type Reset settings = 0000_0000 Bit 7 6:4 Name Reserved LFS[2:0] Read returns zero. Linefeed Shadow. This register reflects the actual realtime linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g., when linefeed equals ringing state, LFS will equal on-hook transmission state during ringing silent period and ringing state during ring burst). 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Read returns zero. Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Function D7 D6 D5 LFS[2:0] R D4 D3 D2 D1 LF[2:0] R/W D0
3 2:0
Reserved LF[2:0]
Preliminary Rev. 0.9
85
Si3 21 0/Si3 211/Si321 2
Register 65. External Bipolar Transistor Control Bit Name Type D7 D6 SQH R/W D5 CBY R/W D4 ETBE R/W D3 D2 D1 D0
ETBO[1:0] R/W
ETBA[1:0] R/W
Reset settings = 0110_0001 Bit 7 6 Name Reserved SQH Read returns zero. Audio Squelch. 0 = No squelch. 1 = STIPAC and SRINGAC pins squelched. Capacitor Bypass. 0 = Capacitors CP (C1) and CM (C2) in circuit. 1 = Capacitors CP (C1) and CM (C2) bypassed. External Transistor Bias Enable. 0 = Bias disabled. 1 = Bias enabled. External Transistor Bias Levels--On-Hook Transmission State. DC bias current which flows through external BJTs in the on-hook transmission state. Increasing this value increases the compliance of the AC longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved External Transistor Bias Levels--Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the AC longitudinal balance circuit. 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = Reserved Function
5
CBY
4
ETBE
3:2
ETBO[1:0]
1:0
ETBA[1:0]
86
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 66. Battery Feed Control SI3210 Bit Name Type Reset settings = 0000_0011 Si3211/Si3212 Bit Name Type Reset settings = 0000_0110 Bit 7:5 4 Name Reserved VOV Read returns zero. Overhead Voltage Range Increase. (See Figure 15 on page 29.) This bit selects the programmable range for VOV, which is defined in indirect Register 41. 0 = VOV = 0 V to 9 V 1 = VOV = 0 V to 13.5 V VBAT Manual Setting (SI3210 only). When EXTBAT = 0: 0 = Normal operation 1 = VBAT tracks VBATH register. When EXTBAT = 1, FVBAT is forced to 0. Si3211/Si3212 = Read returns 0; it cannot be written. 2 EXTBAT DC-to-DC Converter/External Battery Select (SI3210 only). This bit selects battery voltage sourcing mode. 0 = DC-to-DC converter mode selected. 1 = External battery switching mode selected. Si3211/Si3212 = Read returns 1; it cannot be written. Battery Feed Select. When EXTBAT = 1, this bit selects between high and low battery supplies. 0 = Low battery selected (DCSW pin low). 1 = High battery selected (DCSW pin high). DC-to-DC Converter Tracking Mode (SI3210 only). When EXTBAT = 0, this bit selects tracking mode for DC-to-DC converter. 0 = |VBAT| will not decrease below VBATL. 1 = VBAT tracks VRING. Si3211/Si3212 = Reserved. Function D7 D6 D5 D4 VOV R/W D3 D2 D1 BATSL R/W D0 D7 D6 D5 D4 VOV R/W D3 FVBAT R/W D2 EXTBAT R/W D1 BATSL R/W D0 TRACK R/W
3
FVBAT
1
BATSL
0
TRACK
Preliminary Rev. 0.9
87
Si3 21 0/Si3 211/Si321 2
Register 67. Automatic/Manual Control Bit Name Type D7 D6 MNCM R/W D5 MNDIF R/W D4 SPDS R/W D3 ABAT R/W D2 AORD R/W D1 AOLD R/W D0 AOPN R/W
Reset settings = 0001_1111 Bit 7 6 Name Reserved MNCM Read returns zero. Common Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. Differential Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control (forces differential voltage to follow VOC value). Speed-Up Mode Enable. 0 = Speed-up disabled. 1 = Automatic speed-up. Battery Feed Automatic/Manual Select. 0 = Automatic mode disabled. 1 = Automatic mode enabled (automatic switching to low battery in off-hook state). Automatic/Manual Ring Trip Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon ring trip detect. Automatic/Manual Loop Closure Detect. 0 = Manual mode. 1 = Enter off-hook active state automatically upon loop closure detect. Power Alarm Automatic/Manual Detect. 0 = Manual mode. 1 = Enter open state automatically upon power alarm. Function
5
MNDIF
4
SPDS
3
ABAT
2
AORD
1
AOLD
0
AOPN
88
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 68. Loop Closure/Ring Trip Detect Status Bit Name Type Reset settings = 0000_0000 Bit 7:3 2 Name Reserved DBIRAW Read returns zero. Ring Trip/Loop Closure Unfiltered Output. State of this bit reflects the realtime output of ring trip and loop closure detect circuits before debouncing. 0 = Ring trip/loop closure threshold exceeded. 1 = Ring trip/loop closure threshold not exceeded. Ring Trip Detect Indicator (Filtered Output). 0 = Ring trip detect has not occurred. 1 = Ring trip detect occurred. Loop Closure Detect Indicator (Filtered Output). 0 = Loop closure detect has not occurred. 1 = Loop closure detect has occurred. Function D7 D6 D5 D4 D3 D2 DBIRAW R D1 RTP R D0 LCR R
1
RTP
0
LCR
Register 69. Loop Closure Debounce Interval Bit Name Type Reset settings = 0000_1010 Bit 7 6:0 Name Reserved LCDI[6:0] Read returns zero. Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Function D7 D6 D5 D4 D3 LCDI[6:0] R/W D2 D1 D0
Preliminary Rev. 0.9
89
Si3 21 0/Si3 211/Si321 2
Register 70. Ring Trip Detect Debounce Interval Bit Name Type Reset settings = 0000_1010 Bit 7 6:0 Name Reserved RTDI[6:0] Read returns zero. Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. Function D7 D6 D5 D4 D3 RTDI[6:0] R/W D2 D1 D0
Register 71. Loop Current Limit Bit Name Type Reset settings = 0000_0000 Bit 7:3 2:0 Name Reserved ILIM[2:0] Read returns zero. Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07) in 3 mA steps. Function D7 D6 D5 D4 D3 D2 D1 ILIM[2:0] R/W D0
90
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 72. On-Hook Line Voltage Bit Name Type D7 D6 VSGN R/W D5 D4 D3 D2 D1 D0
VOC[5:0] R/W
Reset settings = 0010_0000 Bit 7 6 Name Reserved VSGN Read returns zero. On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity (VTIP-VRING). 0 = VTIP-VRINGis positive 1 = VTIP-VRING is negative On-Hook Line Voltage. The value written to this register sets the on-hook line voltage (VTIP-VRING). Value may be set between 0 V (0x00) and 94.5 V (0x3F) in 1.5 V steps. Default value = 48 V. Function
5:0
VOC[5:0]
Register 73. Common Mode Voltage Bit Name Type Reset settings = 0000_0010 Bit 7:6 5:0 Name Reserved VCM[5:0] Read returns zero. Common Mode Voltage. The value written to this register sets VTIP for forward active and forward on-hook transmission states and VRING for reverse active and reverse on-hook transmission states. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -3 V. Function D7 D6 D5 D4 D3 D2 D1 D0
VCM[5:0] R/W
Preliminary Rev. 0.9
91
Si3 21 0/Si3 211/Si321 2
Register 74. High Battery Voltage Bit Name Type Reset settings = 0011_0010 Bit 7:6 5:0 Name Reserved VBATH[5:0] Read returns zero. High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -75 V. When EXTBAT = 1, VBATH must be set equal to externally supplied VBATH input voltage. Function D7 D6 D5 D4 D3 D2 D1 D0
VBATH[5:0] R/W
Register 75. Low Battery Voltage Bit Name Type Reset settings = 0001_0000 Bit 7:6 5:0 Name Reserved VBATL[5:0] Read returns zero. Low Battery Voltage. The value written to this register sets low battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and -94.5 V (0x3F) in 1.5 V steps. Default value = -24 V. When EXTBAT = 1, VBATL must be set equal to externally supplied VBATL input voltage. Function D7 D6 D5 D4 D3 D2 D1 D0
VBATL[5:0] R/W
92
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 76. Power Monitor Pointer Bit Name Type Reset settings = 0000_0000 Bit 7:3 2:0 Name Reserved PWRMP[2:0] Read returns zero. Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. 000 = Q1 001 = Q2 010 = Q3 011 = Q4 100 = Q5 101 = Q6 110 = Undefined 111 = Undefined Function D7 D6 D5 D4 D3 D2 D1 PWRMP[2:0] R/W D0
Register 77. Line Power Output Monitor Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name PWROM[7:0] Function Line Power Output Monitor. This register reports the realtime power output of the transistor selected using PWRMP. The range is 0 W (0x00) to 6 W (0xFF) in 23.4 mW steps for Q1, Q2, Q5, and Q6. The range is 0 W (0x00) to 0.7 W (0xFF) in 2.76 mW steps for Q3 and Q4. D7 D6 D5 D4 D3 D2 D1 D0
PWROM[7:0] R
Preliminary Rev. 0.9
93
Si3 21 0/Si3 211/Si321 2
Register 78. Loop Voltage Sense Bit Name Type D7 D6 LVSP R D5 D4 D3 LVS[5:0] R D2 D1 D0
Reset settings = 0000_0000 Bit 7 6 Name Reserved LVSP Read returns zero. Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (VTIP - VRING). 0 = Positive loop voltage (VTIP > VRING). 1 = Negative loop voltage (VTIP < VRING). Loop Voltage Sense Magnitude. This register reports the magnitude of the differential loop voltage (VTIP-VRING). The range is 0 V to 94.5 V in 1.5 V steps. Function
5:0
LVS[5:0]
Register 79. Loop Current Sense Bit Name Type D7 D6 LCSP R D5 D4 D3 LCS[5:0] R D2 D1 D0
Reset settings = 0000_0000 Bit 7 6 Name Reserved LCSP Read returns zero. Loop Current Sense Polarity. This register reports the polarity of the loop current. 0 = Positive loop current (forward direction). 1 = Negative loop current (reverse direction). Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range is 0 mA to 78.75 mA in 1.25 mA steps. Function
5:0
LCS[5:0]
94
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 80. TIP Voltage Sense Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VTIP[7:0] Function TIP Voltage Sense. This register reports the realtime voltage at TIP with respect to ground. The range is 0 V (0x00) to -95.625 V (0xFF) in .375 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VTIP[7:0] R
Register 81. RING Voltage Sense Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VRING[7:0] Function RING Voltage Sense. This register reports the realtime voltage at RING with respect to ground. The range is 0 V (0x00) to -95.625 V (0xFF) in .375 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VRING[7:0] R
Register 82. Battery Voltage Sense 1 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VBATS1[7:0] Function Battery Voltage Sense 1. This register is one of two registers that reports the realtime voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.625 V (0xFF) in .375 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VBATS1[7:0] R
Preliminary Rev. 0.9
95
Si3 21 0/Si3 211/Si321 2
Register 83. Battery Voltage Sense 2 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name VBATS2[7:0] Function Battery Voltage Sense 2. This register is one of two registers that reports the realtime voltage at VBAT with respect to ground. The range is 0 V (0x00) to -95.625 V (0xFF) in .375 V steps. D7 D6 D5 D4 D3 D2 D1 D0
VBATS2[7:0] R
Register 84. Transistor 1 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ1[7:0] Function Transistor 1 Current Sense. This register reports the realtime current through Q1. The range is 0 A (0x00) to 79.7 mA (0xFF) in .31 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. D7 D6 D5 D4 IQ1[7:0] R D3 D2 D1 D0
Register 85. Transistor 2 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ2[7:0] Function Transistor 2 Current Sense. This register reports the realtime current through Q2. The range is 0 A (0x00) to 79.7 mA (0xFF) in .31 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. D7 D6 D5 D4 IQ2[7:0] R D3 D2 D1 D0
96
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 86. Transistor 3 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ3[7:0] Function Transistor 3 Current Sense. This register reports the realtime current through Q3. The range is 0 A (0x00) to 9.45 mA (0xFF) in .037 mA steps. D7 D6 D5 D4 IQ3[7:0] R D3 D2 D1 D0
Register 87. Transistor 4 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ4[7:0] Function Transistor 4 Current Sense. This register reports the realtime current through Q4. The range is 0 A (0x00) to 9.45 mA (0xFF) in .037 mA steps. D7 D6 D5 D4 IQ4[7:0] R D3 D2 D1 D0
Register 88. Transistor 5 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ5[7:0] Function Transistor 5 Current Sense. This register reports the realtime current through Q5. The range is 0 A (0x00) to 79.7 mA (0xFF) in .31 mA steps. D7 D6 D5 D4 IQ5[7:0] R D3 D2 D1 D0
Preliminary Rev. 0.9
97
Si3 21 0/Si3 211/Si321 2
Register 89. Transistor 6 Current Sense Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name IQ6[7:0] Function Transistor 6 Current Sense. This register reports the realtime current through Q6. The range is 0 A (0x00) to 79.7 mA (0xFF) in .31 mA steps. D7 D6 D5 D4 IQ6[7:0] R D3 D2 D1 D0
Register 92. DC-to-DC Converter PWM Period SI3210 Bit Name Type Reset settings = 1111_1111 Si3211/Si3212 Bit Name Type Reset settings = xxxx_xxxx Bit 7:0 Name DCN[7:0] Function DC-to-DC Converter Period. This bit sets the PWM period for the DC-to-DC converter. The range is 0 seconds (0x00) to 15.564 s (0xFF) in 61.035 ns steps. Si3211/Si3212 = Reserved D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DCN[7:0] R/W
98
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 93. DC-to-DC Converter Switching Delay SI3210 Bit Name Type D7 DCCAL R/W D6 D5 DCPOL R/W D4 D3 D2 DCTOF[4:0] R/W D1 D0
Reset settings = 0001_0100 Si3211/Si3212 Bit Name Type Reset settings = xxxx_xxxx Bit 7 Name DCCAL Function DC-to-DC Converter Peak Current Monitor Calibration Status (SI3210 only). Writing a one to this bit starts the DC-to-DC converter peak current monitor calibration routine. 0 = Normal operation. 1 = Calibration being performed. Si3211/Si3212 = Reserved. Read returns zero. DC-to-DC Converter Feed Forward Pin (DCFF) Polarity (SI3210 only). 0 = DCFF pin polarity is opposite of DCDRV pin. 1 = DCFF pin polarity is same as DCDRV pin. Si3211/Si3212 = Reserved. DC-to-DC Converter Minimum Off Time (SI3210 only). This register sets the minimum off time for the pulse width modulated DC-to-DC converter control. TOFF = (DCTOF + 4) 61.035 ns. Si3211/Si3212 = Reserved.
"
D7
D6
D5
D4
D3
D2
D1
D0
6 5
Reserved DCPOL
4:0
DCTOF[4:0]
Preliminary Rev. 0.9
99
Si3 21 0/Si3 211/Si321 2
Register 94. DC-to-DC Converter PWM Pulse Width SI3210 Bit Name Type Reset settings = 0000_0000 Si3211/Si3212 Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name DCPW[7:0] Function DC-to-DC Converter Pulse Width (SI3210 only). Pulse width of DCDRV is given by PW = (DCPW - DCTOF - 4) 61.035 ns. Si3211/Si3212 = Reserved.
"
D7
D6
D5
D4
D3
D2
D1
D0
DCPW[7:0] R
D7
D6
D5
D4
D3
D2
D1
D0
100
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 96. Calibration Control/Status Register 1 Bit Name Type D7 D6 CAL R/W D5 CALSP R/W D4 CALR R/W D3 CALT R/W D2 CALD R/W D1 CALC R/W D0 CALIL R/W
Reset settings = 0001_1111 Bit 7 6 Name Reserved CAL Read returns zero. Calibration Control/Status Bit. Setting this bit begins calibration of the entire system. 0 = Normal operation or calibration complete. 1 = Calibration in progress. Calibration Speedup. Setting this bit shortens the time allotted for VBAT settling at the beginning of the calibration cycle. 0 = 300 ms 1 = 30 ms RING Gain Mismatch Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. TIP Gain Mismatch Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Differential DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode DAC Gain Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ILIM Calibration. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Function
5
CALSP
4
CALR
3
CALT
2
CALD
1
CALC
0
CALIL
Preliminary Rev. 0.9
101
Si3 21 0/Si3 211/Si321 2
Register 97. Calibration Control/Status Register 2 Bit Name Type Reset settings = 0001_1111 Bit 7:5 4 Name Reserved CALM1 Read returns zero. Monitor ADC Calibration 1. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Monitor ADC Calibration 2. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. DAC Calibration. Setting this bit begins calibration of the audio DAC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. ADC Calibration. Setting this bit begins calibration of the audio ADC offset. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Common Mode Balance Calibration. Setting this bit begins calibration of the AC longitudinal balance. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. Function D7 D6 D5 D4 CALM1 R/W D3 CALM2 R/W D2 CALDAC R/W D1 CALADC R/W D0 CALCM R/W
3
CALM2
2
CALDAC
1
CALADC
0
CALCM
102
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 98. RING Gain Mismatch Calibration Result Bit Name Type Reset settings = 0001_0000 Bit 7:5 4:0 Name Reserved CALGMR[4:0] Read returns zero. Gain Mismatch of IE Tracking Loop for RING Current. Function D7 D6 D5 D4 D3 D2 CALGMR[4:0] R/W D1 D0
Register 99. TIP Gain Mismatch Calibration Result Bit Name Type Reset settings = 0001_0000 Bit 7:5 4:0 Name Reserved CALGMT[4:0] Read returns zero. Gain Mismatch of IE Tracking Loop for TIP Current. Function D7 D6 D5 D4 D3 D2 CALGMT[4:0] R/W D1 D0
Register 100. Differential Loop Current Gain Calibration Result Bit Name Type Reset settings = 0001_0001 Bit 7:5 4:0 Name Reserved CALGD[4:0] Read returns zero. Differential DAC Gain Calibration Result. Function D7 D6 D5 D4 D3 D2 CALGD[4:0] R/W D1 D0
Preliminary Rev. 0.9
103
Si3 21 0/Si3 211/Si321 2
Register 101. Common Mode Loop Current Gain Calibration Result Bit Name Type Reset settings = 0001_0001 Bit 7:5 4:0 Name Reserved CALGC[4:0] Read returns zero. Common Mode DAC Gain Calibration Result. Function D7 D6 D5 D4 D3 D2 CALGC[4:0] R/W D1 D0
Register 102. Current Limit Calibration Result Bit Name Type Reset settings = 0000_1000 Bit 7:5 3:0 Name Reserved CALGIL[3:0] Read returns zero. Current Limit Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
CALGIL[3:0] R/W
Register 103. Monitor ADC Offset Calibration Result Bit Name Type Reset settings = 1000_1000 Bit 7:4 3:0 Name CALMG1[3:0] CALMG2[3:0] Function Monitor ADC Offset Calibration Result 1. Monitor ADC Offset Calibration Result 2. D7 D6 D5 D4 D3 D2 D1 D0
CALMG1[3:0] R/W
CALMG2[3:0] R/W
104
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 104. Analog DAC/ADC Offset Bit Name Type Reset settings = 0000_0000 Bit 7:4 3 2 1 0 Name Reserved DACP DACN ADCP ADCN Read returns zero. Positive Analog DAC Offset. Negative Analog DAC Offset. Positive Analog ADC Offset. Negative Analog ADC Offset. Function D7 D6 D5 D4 D3 DACP R/W D2 DACN R/W D1 ADCP R/W D0 ADCN R/W
Register 105. DAC Offset Calibration Result Bit Name Type Reset settings = 0000_0000 Bit 7:0 Name DACOF[7:0] DAC Offset Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
DACOF[7:0] R/W
Register 106. Common Mode Calibration Result Bit Name Type Reset settings = 0010_0000 Bit 7:6 5:0 Name Reserved CMBAL[5:0] Read returns zero. Common Mode Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
CMBAL[5:0]
Preliminary Rev. 0.9
105
Si3 21 0/Si3 211/Si321 2
Register 107. DC Peak Current Monitor Calibration Result Bit Name Type Reset settings = 0000_1000 Bit 7:4 3:0 Name Reserved CMDCPK[3:0] Read returns zero. DC Peak Current Monitor Calibration Result. Function D7 D6 D5 D4 D3 D2 D1 D0
CMDCPK[3:0] R/W
106
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Register 108. Enhancement Enable
Note: The Enhancement Enable register and associated features are available in silicon revisions C and later.
SI3210 Bit Name Type D7 ILIMEN R/W D6 FSKEN R/W D5 DCSU R/W D4 ZSEXT R/W D3 SWDB R/W D2 LCVE R/W D1 DCFIL R/W D0 HYSTEN R/W
Reset settings = 0000_0000 Si3211/Si3212 Bit Name Type D7 ILIMEN R/W D6 FSKEN R/W D5 D4 ZSEXT R/W D3 SWDB R/W D2 LCVE R/W D1 D0 HYSTEN R/W
Reset settings = 0000_0000 Bit 7 Name ILIMEN Function Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time to a DC linefeed state. 0 = The value programmed in ILIM (direct Register 71) is used. 1 = The maximum differential loop current limit is temporarily increased to 41 mA. FSK Generation Enhancement. When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are used for FSK generation (indirect registers 99-104). Audio tones are generated using this new higher frequency, and oscillator 1 active and inactive timers have a finer bit resolution of 41.67 s. This provides greater resolution during FSK caller ID signal generation. 0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always used. 1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only when REL = 1; otherwise clocked at 8 kHz. DC-to-DC Converter Control Speedup (SI3210 only). When enabled, this bit invokes a multi-threshold error control algorithm which allows the DC-to-DC converter to adjust more quickly to voltage changes. 0 = Normal control algorithm used. 1 = Multi-threshold error control algorithm used.
6
FSKEN
5
DCSU
Preliminary Rev. 0.9
107
Si3 21 0/Si3 211/Si321 2
Bit 4 Name ZSEXT Function Impedance Internal Reference Resistor Disable. When enabled, this bit removes the internal reference resistor used to synthesize AC impedances for 600 + 2.1 F and 900 + 2.16 F so that an external resistor reference may be used. 0 = Internal resistor used to generate 600 + 2.1 F and 900 + 2.16 F impedances. 1 = Internal resistor removed from circuit. Battery Switch Debounce. When enabled, this bit allows debouncing of the battery switching circuit only when transitioning from VBATH to VBATL external battery supplies (EXTBAT = 1). 0 = No debounce used. 1 = 60 ms debounce period used. Voltage-Based Loop Closure. Enables loop closure to be determined by the TIP-to-RING voltage rather than loop current. 0 = Loop closure determined by loop current. 1 = Loop closure determined by TIP-to-RING voltage. DC-to-DC Converter Squelch (SI3210 only). When enabled, this bit squelches noise in the audio band from the DC-to-DC converter control loop. 0 = Voice band squelch disabled. 1 = Voice band squelch enabled. Loop Closure Hysteresis Enable. When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by indirect registers 28 and 43, respectively. 0 = Loop closure hysteresis disabled. 1 = Loop closure hysteresis enabled.
3
SWDB
2
LCVE
1
DCFIL
0
HYSTEN
108
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update. A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of 16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
DTMF Decoding (SI3210 and Si3211 only)
All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state.
Table 28. DTMF Indirect Registers Summary
Addr. D15 0 1 2 3 4 5 6 7 8 9 10 11 12 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ROW0[15:0] ROW1[15:0] ROW2[15:0] ROW3[15:0] COL[15:0] FWDTW[15:0] REVTW[15:0] ROWREL[15:0] COLREL[15:0] ROW2[15:0] COL2[15:0] PWRMIN[15:0] HOTL[15:0]
Table 29. DTMF Indirect Registers Description
Addr. 0 Description DTMF Row 0 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of power in row 0 to total power in the row band is greater than ROW0, then a row 0 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Row 1 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 1 DTMF detection. If the ratio of power in row 1 to total power in the row band is greater than ROW1, then a row 1 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. Reference Page 39
1
39
Preliminary Rev. 0.9
109
Si3 21 0/Si3 211/Si321 2
Table 29. DTMF Indirect Registers Description (Continued)
Addr. 2 Description DTMF Row 2 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 2 DTMF detection. If the ratio of power in row 2 to total power in the row band is greater than ROW2, then a row 2 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Row 3 Peak Magnitude Pass Ratio Threshold. This register sets the minimum power ratio threshold for row 3 DTMF detection. If the ratio of power in row 3 to total power in the row band is greater than ROW3, then a row 3 signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Column Peak Magnitude Pass Threshold. This register sets the minimum power ratio threshold for column DTMF detection; all columns use the same threshold. If the ratio of power in a particular column to total power in the column band is greater than COL, then a column detect for that particular column signal is detected. A value of 0x7FF0 corresponds to a 1.0 ratio. DTMF Forward Twist Threshold. This register sets the threshold for the power ratio of row power to column power. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Reverse Twist Threshold. This register sets the threshold for the power ratio of column power to row power. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Row Ratio Threshold. This register sets the threshold for the power ratio of highest power row to the other rows. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Column Ratio Threshold. This register sets the threshold for the power ratio of highest power column to the other columns. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Row Second Harmonic Threshold. This register sets the threshold for the power ratio of peak row tone to its second harmonic. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Column Second Harmonic Threshold. This register sets the threshold for the power ratio of peak column tone to its second harmonic. A value of 0x7F0 corresponds to a 1.0 ratio. DTMF Power Minimum Threshold. This register sets the threshold for the minimum total power in the DTMF calculation, under which the calculation is ignored. DTMF Hot Limit Threshold. This register sets the two-step AGC in the DTMF path. Reference Page 39
3
39
4
39
5
39
6
39
7
39
8
39
9
39
10
39
11
39
12
39
110
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
Oscillators
See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state.
Table 30. Oscillator Indirect Registers Summary
Addr. D15 13 14 15 16 17 18 19 20 21 22 23 24 25 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OSC1[15:0] OSC1X[15:0] OSC1Y[15:0] OSC2[15:0] OSC2X[15:0] OSC2Y[15:0] ROFF[15:0] RCO[15:0] RNGX[15:0] RNGY[15:0] PLSD[15:0] PLSX[15:0] PLSCO[15:0]
Table 31. Oscillator Indirect Registers Description
Addr. 13 14 15 16 17 18 19 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. Oscillator 1 Amplitude Register. Sets tone generator 1 signal amplitude. Oscillator 1 Initial Phase Register. Sets initial phase of tone generator 1 signal. Oscillator 2 Frequency Coefficient. Sets tone generator 2 frequency. Oscillator 2 Amplitude Register. Sets tone generator 2 signal amplitude. Oscillator 2 Initial Phase Register. Sets initial phase of tone generator 2 signal. Ringing Oscillator DC Offset. Sets DC offset component (VTIP-VRING) to ringing waveform. The range is 0 to 94.5 V in 1.5 V increments. Ringing Oscillator Frequency Coefficient. Sets ringing generator frequency. Description Reference Page 32 32 32 32 32 32 34
20
34
Preliminary Rev. 0.9
111
Si3 21 0/Si3 211/Si321 2
Table 31. Oscillator Indirect Registers Description (Continued)
Addr. 21 22 23 24 25 Description Ringing Oscillator Amplitude Register. Sets ringing generator signal amplitude. Ringing Oscillator Initial Phase Register. Sets initial phase of ringing generator signal. Pulse Metering Oscillator Attack/Decay Ramp Rate. Sets pulse metering attack/decay ramp rate. Pulse Metering Oscillator Amplitude Register. Sets pulse metering generator signal amplitude. Pulse Metering Oscillator Frequency Coefficient. Sets pulse metering generator frequency. Reference Page 34 34 38 38 38
Digital Programmable Gain/Attenuation
See functional description sections of digital programmable gain/attenuation for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 32. Digital Programmable Gain/Attenuation Indirect Registers Summary
Addr. D15 26 27 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DACG[11:0] ADCG[11:0]
Table 33. Digital Programmable Gain/Attenuation Indirect Registers Description
Addr. 26 Description Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively multiplied by DACG to achieve gain/attenuation. A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Transmit Path Analog to Digital Converter Gain/Attenuation. This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Reference Page 40
27
40
112
Preliminary Rev. 0.9
SI3210/Si3211/Si3212
SLIC Control
See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes.
Table 34. SLIC Control Indirect Registers Summary
Addr. D15 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
*Note: SI3210 only.
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LCRT[5:0] RPTP[5:0] CML[5:0] CMH[5:0] PPT12[7:0] PPT34[7:0] PPT56[7:0] NCLR[12:0] NRTP[12:0] NQ12[12:0] NQ34[12:0] NQ56[12:0] VCMR[3:0] VMIND[3:0]* LCRTL[5:0]
Table 35. SLIC Control Indirect Registers Description
Addr. 28 Description Loop Closure Threshold. Loop closure detection threshold. This register defines the upper bounds threshold if hysteresis is enabled (direct Register 108, bit 0). Ring Trip Threshold. Ring trip detection threshold during ringing. Common Mode Minimum Threshold for Speed-Up. Common Mode Maximum Threshold for Speed-Up. Power Alarm Threshold for Transistors Q1 and Q2. Power Alarm Threshold for Transistors Q3 and Q4. Power Alarm Threshold for Transistors Q5 and Q6. Loop Closure Filter Coefficient. 25 25 25 27 Reference Page 27
29 30 31 32 33 34 35
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Table 35. SLIC Control Indirect Registers Description (Continued)
Addr. 36 37 38 39 40 41 Ring Trip Filter Coefficient. Thermal Low Pass Filter Pole for Transistors Q1 and Q2. Thermal Low Pass Filter Pole for Transistors Q3 and Q4. Thermal Low Pass Filter Pole for Transistors Q5 and Q6. Common Mode Bias Adjust During Ringing. Recommended value of 6 decimal. DC-to-DC Converter VOV Voltage (SI3210 only). This register sets the overhead voltage, VOV, to be supplied by the DC-to-DC converter. When the VOV bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V (VMIND = 0 to 6h). When the VOV bit = 1, VOV should be set between 0 and 13.5 V (VMIND = 0 to 9h). 42 43 Reserved. Loop Closure Threshold--Lower Bound. This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of direct Register 108. 27 Description Reference Page 37 25 25 25 34 28
FSK Control
For detailed instructions on FSK signal generation, refer to "Application Note 32: FSK Generation" (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6).
Table 36. FSK Control Indirect Registers Summary
Addr. D15 99 100 101 102 103 104 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FSK0X[15:0] FSK0[15:0] FSK1X[15:0] FSK1[15:0] FSK01[15:0] FSK10[15:0]
Table 37. FSK Control Indirect Registers Description
Addr. 99 Description FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a space or "0". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. Reference Page 34 and AN32
100
34 and AN32
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Table 37. FSK Control Indirect Registers Description (Continued)
Addr. 101 Description FSK Amplitude Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. FSK Frequency Coefficient for Mark. When FSKEN = 1 and REL = 1, this register sets the frequency to be used when generating a mark or "1". When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1. FSK Transition Parameter from 0 to 1. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a space (0) to a mark (1). FSK Transition Parameter from 1 to 0. When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a mark (1) to a space (0). Reference Page 34 and AN32
102
34 and AN32
103
34 and AN32
104
34 and AN32
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Pin Descriptions: SI3210/11/12
CS INT PCLK DRX DTX FSYNC RESET SDCH/DIO1 SDCL/DIO2 VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC STIPE SVBAT SRINGE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
SCLK SDI SDO SDITHRU
DCDRV/DCSW
DCFF/DOUT TEST GNDD VDDD ITIPN ITIPP VDDA2 IRINGP IRINGN IGMP GNDA IGMN SRINGAC STIPAC
Pin # 1
Pin Name CS
Description Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. Interrupt. Maskable interrupt output. Open drain output for wire-ORed operation. PCM Bus Clock. Clock input for PCM bus timing. Receive PCM Data. Input data from PCM bus. Transmit PCM Data. Output data to PCM bus. Frame Synch. 8 kHz frame synchronization signal for the PCM bus. May be short or long pulse format. Reset. Active low input. Hardware reset used to place all control registers in the default state. DC Monitor/General Purpose I/O. DC-to-DC converter monitor input used to detect overcurrent situations in the converter (SI3210 only). General purpose I/O in external battery mode.
2 3 4 5 6 7 8
INT PCLK DRX DTX FSYNC RESET SDCH/DIO1
9
SDCL/DIO2
DC Monitor/General Purpose I/O. DC-to-DC converter monitor input used to detect overcurrent situations in the converter (SI3210 only). General purpose I/O in external battery mode.
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Pin # 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin Name VDDA1 IREF CAPP QGND CAPM STIPDC SRINGDC STIPE SVBAT SRINGE STIPAC SRINGAC IGMN GNDA IGMP IRINGN IRINGP VDDA2 ITIPP ITIPN Analog Supply Voltage. Analog power supply for internal analog circuitry. Current Reference. Connects to an external resistor used to provide a high accuracy reference current. SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. Component Reference Ground. SLIC Stabilization Capacitor. Capacitor used in low pass filter to stabilize SLIC feedback loops. TIP Sense. Analog current input used to sense voltage on the TIP lead. RING Sense. Analog current input used to sense voltage on the RING lead. TIP Emitter Sense. Analog current input used to sense voltage on the Q6 emitter lead. VBAT Sense. Analog current input used to sense voltage on DC-to-DC converter output voltage lead. RING Emitter Sense. Analog current input used to sense voltage on the Q5 emitter lead. TIP Transmit Input. Analog AC input used to detect voltage on the TIP lead. RING Transmit Input. Analog AC input used to detect voltage on the RING lead. Transconductance Amplifier External Resistor. Negative connection for transconductance gain setting resistor. Analog Ground. Ground connection for internal analog circuitry. Transconductance Amplifier External Resistor. Positive connection for transconductance gain setting resistor. Negative Ring Current Control. Analog current output driving Q3. Positive Ring Current Control. Analog current output driving Q2. Analog Supply Voltage. Analog power supply for internal analog circuitry. Positive TIP Current Control. Analog current output driving Q1. Negative TIP Current Control. Analog current output driving Q4. Description
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Pin # 30 31 32 Pin Name VDDD GNDD TEST Digital Supply Voltage. Digital power supply for internal digital circuitry. Digital Ground. Ground connection for internal digital circuitry. Test. Enables test modes for Silicon Labs internal testing. This pin should always be tied to ground for normal operation. 33 DCFF/DOUT DC Feed-Forward/High Current General Purpose Output. Feed-forward drive of external bipolar transistors to improve DC-to-DC converter efficiency (SI3210 only). High current output pin in external battery mode. 34 DCDRV/DCSW DC Drive/Battery Switch. DC-to-DC converter control signal output which drives external bipolar transistor (SI3210 only). Battery switch control signal output which drives external bipolar transistor in external battery mode. 35 36 37 38 SDITHRU SDO SDI SCLK SDI Passthrough. Cascaded SDI output signal for daisy-chain mode. Serial Port Data Out. Serial port control data output. Serial Port Data In. Serial port control data input. Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. Description
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Ordering Guide
Table 38. Ordering Guide
Chip SI3210-KT SI3210-BT Si3211-KT Si3211-BT Si3212-KT Si3212-BT DC-to-DC Converter ! ! DTMF Decoder ! ! ! ! Package 38-pin TSSOP 38-pin TSSOP 38-pin TSSOP 38-pin TSSOP 38-pin TSSOP 38-pin TSSOP Temperature 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
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Package Outline
Figure 30 illustrates the package details for the ProSLIC. Table 39 lists the values for the dimensions shown in the illustration.
E
H L
B D A e
A1
C
Figure 30. 38-pin Thin Shrink Small Outline Package (TSSOP) Table 39. Package Diagram Dimensions
Inches Symbol A A1 B C D E e H L Min -- 0.002 0.007 0.004 Max 0.047 0.006 0.011 0.008 Millimeters Min -- 0.05 0.17 0.09 Max 1.1 0.15 0.27 0.20
0.381 BSC 0.169 0.177
9.7 BSC 4.30 .5 BSC 6.40 BSC 0.45 0 0.75 8 4.50
.02 BSC 0.252 BSC 0.018 0 0.030 8
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Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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